cdkersey / chdlLinks
A C++ Hardware Description Language and Toolchain
☆23Updated last year
Alternatives and similar repositories for chdl
Users that are interested in chdl are comparing it to the libraries listed below
Sorting:
- C++17 implementation of an AST for Verilog code generation☆24Updated 2 years ago
- A powerful and modern open-source architecture description language.☆42Updated 7 years ago
- A time-predictable processor for mixed-criticality systems☆59Updated 9 months ago
- ☆103Updated 3 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- Debuggable hardware generator☆69Updated 2 years ago
- A Tiny Processor Core☆110Updated last month
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆84Updated 10 months ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆227Updated this week
- Documentation for the BOOM processor☆47Updated 8 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- Visual Simulation of Register Transfer Logic☆101Updated 2 weeks ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆111Updated 3 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated 3 weeks ago
- C++ parsing library for simple formats used in logic synthesis and formal verification☆37Updated last year
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Updated 4 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Chisel library for Unum Type-III Posit Arithmetic☆39Updated 5 months ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Xtext project to parse CoreDSL files☆21Updated 7 months ago
- A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.☆154Updated 5 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- A circuit toolkit☆105Updated 5 years ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆163Updated 2 months ago
- FPGA Assembly (FASM) Parser and Generator☆95Updated 3 years ago
- A Modeling and Verification Platform for SoCs using ILAs☆77Updated last year
- CoreIR Symbolic Analyzer☆74Updated 4 years ago