Implementation of a Systolic Array based sorting engine on an FPGA using Verilog
☆11May 11, 2017Updated 8 years ago
Alternatives and similar repositories for systolic-array-sorting
Users that are interested in systolic-array-sorting are comparing it to the libraries listed below
Sorting:
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 9 years ago
- verilog CNN generator for FPGA☆34Jan 4, 2021Updated 5 years ago
- Conway's Game of Life implemented in Metal and Swift☆14Nov 28, 2017Updated 8 years ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated last year
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Jan 30, 2023Updated 3 years ago
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 4 years ago
- Set of Minimal C Utilities☆16Aug 21, 2015Updated 10 years ago
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated last year
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Sep 22, 2018Updated 7 years ago
- Hardware and software implementation of Sparsely-active SNNs☆22Mar 6, 2026Updated 2 weeks ago
- A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.☆17May 30, 2023Updated 2 years ago
- Support for zScale on Spartan6 FPGAs☆15Aug 3, 2015Updated 10 years ago
- HLS Custom-Precision Floating-Point Library☆13Nov 6, 2017Updated 8 years ago
- first-order deep learning accelerator model☆22Nov 27, 2017Updated 8 years ago
- Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube☆12Feb 13, 2017Updated 9 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆27Jul 4, 2019Updated 6 years ago
- Benchmark of different RL algorithm☆13Dec 8, 2022Updated 3 years ago
- FPU Generator☆20Jul 19, 2021Updated 4 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆23May 20, 2019Updated 6 years ago
- CNN accelerator☆29Jun 11, 2017Updated 8 years ago
- 天猫双12欢乐币自动脚本 配合淘宝低版本☆15Dec 4, 2020Updated 5 years ago
- An automated HDC platform☆11Mar 6, 2026Updated last week
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆86Nov 26, 2025Updated 3 months ago
- Tensorflow cheat sheet for reference☆10Jan 15, 2018Updated 8 years ago
- Hybrid Memory Cube Simulation & Research Infrastructure☆17Jun 9, 2025Updated 9 months ago
- 历年CSP考试 题解☆14Apr 14, 2020Updated 5 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆25Nov 2, 2015Updated 10 years ago
- A DSL for Systolic Arrays☆83Dec 14, 2018Updated 7 years ago
- Use a CNN architecture to segment and classify 3d meshes☆17May 1, 2016Updated 9 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆23Aug 10, 2018Updated 7 years ago
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- This repository contains full code of Softmax Layer in Verilog☆21Jul 29, 2020Updated 5 years ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆22Nov 27, 2025Updated 3 months ago
- ☆20Mar 26, 2019Updated 6 years ago
- System on Chip toolkit for nMigen☆19Apr 29, 2020Updated 5 years ago
- Implementation of DeepID2☆18Sep 5, 2016Updated 9 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆37Dec 22, 2023Updated 2 years ago
- R interface to Tensorflow via skflow☆18May 13, 2016Updated 9 years ago
- Template for project1 TPU☆23May 1, 2021Updated 4 years ago