themathgeek13 / systolic-array-sortingLinks
Implementation of a Systolic Array based sorting engine on an FPGA using Verilog
☆11Updated 8 years ago
Alternatives and similar repositories for systolic-array-sorting
Users that are interested in systolic-array-sorting are comparing it to the libraries listed below
Sorting:
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆12Updated 9 years ago
- CNN accelerator☆27Updated 8 years ago
- A configurable general purpose graphics processing unit for☆11Updated 6 years ago
- ☆27Updated 5 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆21Updated 12 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- Digital IC design and vlsi notes☆12Updated 5 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- ☆73Updated last week
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆30Updated 9 years ago
- NoC based MPSoC☆11Updated 11 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆19Updated 9 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 4 years ago
- Reconfigurable Binary Engine☆17Updated 4 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆13Updated last year
- The official NaplesPU hardware code repository☆18Updated 6 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated last week
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Updated 10 years ago
- double_fpu_verilog☆16Updated 11 years ago
- FPU Generator☆20Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- ☆25Updated 4 years ago
- Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs☆48Updated 8 years ago