Alternatives and similar repositories for super-prove-build:

Users that are interested in super-prove-build are comparing it to the libraries listed below

• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆9Updated 6 months ago
• morenes / AutoCC
  Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…
  ☆17Updated 6 months ago
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆15Updated 4 years ago
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 5 years ago
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆15Updated 6 years ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆11Updated 3 years ago
• iscas-tis / CHA
  ☆19Updated 9 months ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• amahzoon / genmul
  ☆16Updated 4 years ago
• fangwenji / tacas23-wasim
  ☆12Updated 2 years ago
• gpt4rtl / AutoSVA2
  ☆14Updated last year
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆21Updated 3 months ago
• efeslab / hardware-bugbase
  ☆18Updated 10 months ago
• chengyinwu / QuteRTL
  QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification
  ☆15Updated 8 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆42Updated 3 weeks ago
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆48Updated this week
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆22Updated last year
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆22Updated 3 months ago
• CoriolisSP / FuzzBtor2
  Random Generator of Btor2 Files
  ☆10Updated last year
• amahzoon / RevSCA-2.0
  ☆10Updated 5 years ago
• openformal / sva_basics
  This repository is compilation of basics of System Verilog Assertions in context of formal verification
  ☆20Updated 6 years ago
• mit-plv / hemiola
  A Coq framework to support structural design and proof of hardware cache-coherence protocols
  ☆13Updated 2 years ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆33Updated 3 months ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆72Updated 4 years ago
• Moorvan / ChiselFV
  A Formal Verification Framework for Chisel
  ☆18Updated last year
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆34Updated last week
• euphoric-hardware / rtl-simulation-reading
  ☆14Updated last month
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆16Updated 3 weeks ago
• wincle626 / HLS_Legup
  ☆27Updated 7 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated last week