mattvenn / efabless_project_tool
Tool to fetch and parse data about Efabless MPW projects
☆16Updated 2 years ago
Alternatives and similar repositories for efabless_project_tool:
Users that are interested in efabless_project_tool are comparing it to the libraries listed below
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- Time to Digital Converter (TDC)☆30Updated 4 years ago
- Demo board for TT4 and beyond☆20Updated last week
- A reconfigurable logic circuit made of identical rotatable tiles.☆21Updated 3 years ago
- ☆19Updated 4 years ago
- Proof of Concept to learn Amaranth as an entry effort for Supercon's RTL design competition☆10Updated 2 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- A padring generator for ASICs☆25Updated last year
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- ☆33Updated 2 years ago
- SAR ADC on tiny tapeout☆39Updated 3 weeks ago
- Flip flop setup, hold & metastability explorer tool☆32Updated 2 years ago
- System on Chip toolkit for nMigen☆19Updated 4 years ago
- Small footprint and configurable Inter-Chip communication cores☆55Updated last month
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Updated 3 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- IRSIM switch-level simulator for digital circuits☆31Updated 9 months ago
- ☆30Updated 4 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- ☆15Updated 3 months ago
- Cross compile FPGA tools☆22Updated 4 years ago
- Adder in VHDL to test the digital flow using ghdl and GTKwave (front-end) and openlane (back-end). Translated from the original https://g…☆11Updated 3 years ago
- Open Source FPGA toolchain and documentation for QuickLogic devices and eFPGA IP☆36Updated 3 years ago
- ☆36Updated 2 years ago
- Small footprint and configurable HyperBus core☆11Updated 2 years ago
- ☆22Updated 2 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆27Updated last month
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆59Updated 3 years ago
- iCE40 floorplan viewer☆24Updated 6 years ago