chipsalliance / OmnixtendEndpointLinks
Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.
☆18Updated 2 months ago
Alternatives and similar repositories for OmnixtendEndpoint
Users that are interested in OmnixtendEndpoint are comparing it to the libraries listed below
Sorting:
- OmniXtend cache coherence protocol☆82Updated last month
- For contributions of Chisel IP to the chisel community.☆64Updated 9 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆106Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 months ago
- A fault-injection framework using Chisel and FIRRTL☆37Updated 3 months ago
- ☆32Updated 8 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated 2 weeks ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated 3 weeks ago
- Pure digital components of a UCIe controller☆66Updated 3 weeks ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆48Updated 4 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆174Updated 3 weeks ago
- ☆30Updated 2 weeks ago
- Platform Level Interrupt Controller☆41Updated last year
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- ☆63Updated 4 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- ☆17Updated last week
- ☆97Updated last year
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- ☆47Updated 4 months ago
- ☆73Updated this week
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago