Alternatives and similar repositories for OmnixtendEndpoint

Users that are interested in OmnixtendEndpoint are comparing it to the libraries listed below

• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated 3 weeks ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆65Updated 9 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 2 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆89Updated last week
• chipsalliance / tilelink
  ☆34Updated 8 months ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 2 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆50Updated 10 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆120Updated last month
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆107Updated 4 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆43Updated 2 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 5 years ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆73Updated last year
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆177Updated this week
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆46Updated 3 years ago
• pulp-platform / redmule
  ☆73Updated last week
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆114Updated last week
• esa-tu-darmstadt / SCAIE-V-2.0
  ☆15Updated 2 months ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆37Updated 3 months ago
• pulp-platform / cheshire-ihp130-o
  ☆49Updated 5 months ago
• qleenju / PDPU
  PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications
  ☆43Updated 2 years ago
• pulp-platform / ace
  ☆19Updated last month
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 5 years ago
• bsc-loca / sargantana
  ☆107Updated 2 weeks ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 10 months ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆49Updated 4 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 5 months ago