chipsalliance / OmnixtendEndpoint
Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.
☆17Updated this week
Alternatives and similar repositories for OmnixtendEndpoint
Users that are interested in OmnixtendEndpoint are comparing it to the libraries listed below
Sorting:
- For contributions of Chisel IP to the chisel community.☆61Updated 6 months ago
- ☆27Updated last month
- Platform Level Interrupt Controller☆40Updated last year
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆41Updated 2 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆63Updated 11 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆103Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆47Updated 6 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆72Updated 3 weeks ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 4 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆47Updated 4 years ago
- OmniXtend cache coherence protocol☆82Updated 4 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- ☆93Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 2 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated 2 months ago
- Advanced Architecture Labs with CVA6☆59Updated last year
- ☆56Updated 4 years ago
- ☆30Updated 5 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- ☆61Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆99Updated last month
- YosysHQ SVA AXI Properties☆39Updated 2 years ago
- Intel Compiler for SystemC☆23Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 7 months ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated 2 months ago
- General Purpose AXI Direct Memory Access☆49Updated last year
- Chisel Cheatsheet☆33Updated 2 years ago