pku-liang / ksim
☆39Updated last month
Alternatives and similar repositories for ksim:
Users that are interested in ksim are comparing it to the libraries listed below
- A hardware synthesis framework with multi-level paradigm☆36Updated last month
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆57Updated 4 months ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆26Updated last month
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated 11 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆48Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆59Updated 2 months ago
- ☆24Updated last year
- ☆12Updated last month
- ☆52Updated this week
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- CGRA framework with vectorization support.☆24Updated this week
- ☆22Updated 3 months ago
- ☆39Updated this week
- ☆42Updated 10 months ago
- ☆15Updated 2 years ago
- A DSL for Systolic Arrays☆78Updated 6 years ago
- ☆32Updated last week
- An Open-Source Tool for CGRA Accelerators☆58Updated last month
- ILA Model Database☆22Updated 4 years ago
- The official repository of metro-mpi☆15Updated last year
- ☆15Updated 2 years ago
- ☆89Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆66Updated 5 years ago
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆20Updated 7 months ago
- An Open-Source Tool for CGRA Accelerators☆18Updated 9 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆60Updated 7 months ago
- The open-sourced version of BOOM-Explorer☆36Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆102Updated 10 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago