☆53Jan 16, 2025Updated last year
Alternatives and similar repositories for ksim
Users that are interested in ksim are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆38Jan 16, 2025Updated last year
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆38Jan 26, 2026Updated 4 months ago
- ☆17Mar 26, 2025Updated last year
- ☆73May 11, 2026Updated 3 weeks ago
- high-performance RTL simulator☆193Jun 19, 2024Updated last year
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Using e-graphs to synthesize netlists from boolean logic.☆14Jul 26, 2023Updated 2 years ago
- GL0AM GPU Accelerated Gate Level Logic Simulator☆30Feb 11, 2026Updated 3 months ago
- A hardware synthesis framework with multi-level paradigm☆45Jan 10, 2025Updated last year
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆27Nov 26, 2025Updated 6 months ago
- The specification for the FIRRTL language☆66May 31, 2026Updated last week
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆72Jun 2, 2026Updated last week
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆16Mar 3, 2026Updated 3 months ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆122Apr 1, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆20Mar 3, 2026Updated 3 months ago
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆98Apr 18, 2026Updated last month
- (System)Verilog to Chisel translator☆121May 20, 2022Updated 4 years ago
- ☆21May 26, 2025Updated last year
- The official repository of metro-mpi☆18Sep 3, 2025Updated 9 months ago
- Header-only C/C++ static keys to avoid the overhead of conditional branches☆14Feb 10, 2024Updated 2 years ago
- ☆17Feb 24, 2025Updated last year
- A core language for rule-based hardware design 🦑☆173Dec 10, 2025Updated 5 months ago
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated last year
- The 'missing header' for Chisel☆24Feb 5, 2026Updated 4 months ago
- About the source code of "Merging Similar Patterns for Hardware Prefetching" paper, which is accepted in MICRO 2022.☆14Mar 1, 2023Updated 3 years ago
- EQueue Dialect☆42Feb 3, 2022Updated 4 years ago
- BSC Development Workstation (BDW)☆33May 1, 2026Updated last month
- A Hardware Pipeline Description Language☆60Jul 12, 2025Updated 10 months ago
- An open-source EDA infrastructure and tools from netlist to GDS☆514Mar 11, 2026Updated 2 months ago
- Basic chisel difftest environment for RTL design (WIP☆21Mar 8, 2025Updated last year
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ordspecsim: The Swarm architecture simulator☆25Feb 15, 2023Updated 3 years ago
- Hands-On Practical MLIR Tutorial☆787Oct 20, 2023Updated 2 years ago
- This repository is outdated and the related functionality has been migrated to https://github.com/easysoc/easysoc-firrtl☆11Nov 3, 2021Updated 4 years ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆24Mar 31, 2026Updated 2 months ago
- ☆35Nov 6, 2024Updated last year
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- The Chronos FPGA Framework to accelerate ordered applications☆22May 20, 2020Updated 6 years ago