Alternatives and similar repositories for ksim

Users that are interested in ksim are comparing it to the libraries listed below

• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆40Updated 6 months ago
• pku-liang / Hestia
  ☆17Updated 3 months ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆49Updated last year
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆29Updated 5 months ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆73Updated this week
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆59Updated 9 months ago
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆32Updated last year
• ucb-bar / virgo
  Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
  ☆35Updated last month
• ucsc-vama / essent
  high-performance RTL simulator
  ☆168Updated last year
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆55Updated 3 months ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆112Updated last year
• lana555 / dynamatic
  ☆86Updated last year
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆32Updated this week
• pnnl / soda-opt
  ☆46Updated last week
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆122Updated 2 years ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆80Updated 6 years ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆67Updated 2 months ago
• hngenc / stellar
  ☆30Updated 8 months ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆75Updated 6 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆92Updated last year
• cornell-zhang / allo-pldi24-artifact
  Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"
  ☆24Updated last year
• StanfordAHA / aha
  ☆59Updated this week
• CMU-SAFARI / Load-Inspector
  A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…
  ☆21Updated last year
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 2 years ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆68Updated last year
• epfl-vlsc / parendi
  Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU
  ☆22Updated last year
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆133Updated 3 weeks ago
• pku-dasys / easymac
  ☆16Updated 3 years ago