esa-tu-darmstadt / BlueAXI
☆8Updated last year
Related projects ⓘ
Alternatives and complementary repositories for BlueAXI
- RISC-V soft-core PEs for TaPaSCo☆15Updated 5 months ago
- PCI Express controller model☆45Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- Bitstream relocation and manipulation tool.☆39Updated last year
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆18Updated this week
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆14Updated 4 years ago
- ☆36Updated 2 years ago
- YosysHQ SVA AXI Properties☆31Updated last year
- Framework Open EDA Gui☆60Updated this week
- ☆57Updated 3 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆63Updated 2 months ago
- ☆30Updated last year
- Re-coded Xilinx primitives for Verilator use☆41Updated 8 months ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- AXI Formal Verification IP☆19Updated 3 years ago
- A configurable SRAM generator☆40Updated last week
- IEEE 754 single precision floating point library in systemverilog and vhdl☆26Updated last month
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- Platform Level Interrupt Controller☆35Updated 6 months ago
- ☆32Updated last year
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆21Updated 3 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- DUTH RISC-V Superscalar Microprocessor☆28Updated 3 weeks ago
- OPAE porting to Xilinx FPGA devices.☆38Updated 4 years ago
- BlackParrot on Zynq☆25Updated this week
- Sphinx Extension which generates various types of diagrams from Verilog code.☆54Updated last year
- Cross EDA Abstraction and Automation☆35Updated 2 weeks ago
- Equivalence checking with Yosys☆30Updated this week
- An automatic clock gating utility☆40Updated 3 months ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- Open source process design kit for 28nm open process☆43Updated 6 months ago