KULeuven-MICAS / zigzagLinks
HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators
☆181Updated 2 weeks ago
Alternatives and similar repositories for zigzag
Users that are interested in zigzag are comparing it to the libraries listed below
Sorting:
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆156Updated 8 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆74Updated 3 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆163Updated this week
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 7 months ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆237Updated 3 years ago
- STONNE: A Simulation Tool for Neural Networks Engines☆145Updated 7 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆152Updated this week
- Exercises for exploring the Fibertree, Timeloop and Accelergy tools☆114Updated 10 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆72Updated 4 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆84Updated 4 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆43Updated 3 years ago
- Repository to host and maintain SCALE-Sim code☆412Updated last week
- ☆62Updated 10 months ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆180Updated 5 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆31Updated 2 years ago
- ☆84Updated last month
- An Open-Source Tool for CGRA Accelerators☆82Updated 5 months ago
- An integrated CGRA design framework☆91Updated 10 months ago
- FSA: Fusing FlashAttention within a Single Systolic Array☆86Updated 6 months ago
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆117Updated 3 months ago
- An analytical cost model evaluating DNN mappings (dataflows and tiling).☆247Updated last year
- ☆57Updated 7 months ago
- An FPGA Accelerator for Transformer Inference☆93Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆35Updated this week
- ☆57Updated 2 months ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆58Updated 6 months ago
- ☆42Updated last year