Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
☆82Apr 30, 2019Updated 6 years ago
Alternatives and similar repositories for buffets
Users that are interested in buffets are comparing it to the libraries listed below
Sorting:
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆255Oct 6, 2022Updated 3 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆156May 26, 2025Updated 9 months ago
- Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.☆456Feb 19, 2026Updated last week
- A pre-RTL, power-performance model for fixed-function accelerators☆185Jan 17, 2024Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Sep 24, 2021Updated 4 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆64Oct 14, 2025Updated 4 months ago
- RTL implementation of Flex-DPE.☆115Feb 22, 2020Updated 6 years ago
- ☆13Oct 8, 2024Updated last year
- ☆43Mar 31, 2025Updated 11 months ago
- ☆377May 11, 2023Updated 2 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆47Jan 26, 2023Updated 3 years ago
- Repository to host and maintain SCALE-Sim code☆413Feb 2, 2026Updated 3 weeks ago
- Exercises for exploring the Fibertree, Timeloop and Accelergy tools☆115Apr 9, 2025Updated 10 months ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 10 months ago
- Tutorial Material from the SST Team☆25Aug 5, 2025Updated 6 months ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆24Feb 8, 2026Updated 3 weeks ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆85Aug 28, 2023Updated 2 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆25Updated this week
- PyTorchSim is a Comprehensive, Fast, and Accurate NPU Simulation Framework☆91Updated this week
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Updated this week
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 4 years ago
- An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model☆531Jun 25, 2024Updated last year
- ☆36Apr 20, 2021Updated 4 years ago
- Explore the energy-efficient dataflow scheduling for neural networks.☆233Aug 24, 2020Updated 5 years ago
- BookSim 2.0☆400Jun 24, 2024Updated last year
- ☆15Nov 12, 2023Updated 2 years ago
- ☆15Dec 15, 2022Updated 3 years ago
- Synthetic Traffic Models Capturing a Full Range of Cache Coherent Behaviour☆14May 17, 2019Updated 6 years ago
- DRAMSim2: A cycle accurate DRAM simulator☆294Nov 11, 2020Updated 5 years ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆404Feb 6, 2026Updated 3 weeks ago
- McPAT modeling framework☆12Oct 18, 2014Updated 11 years ago
- Relaxed Rust (for cats)☆14Nov 20, 2019Updated 6 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆49Jan 2, 2025Updated last year
- ☆29Oct 20, 2019Updated 6 years ago
- An analytical cost model evaluating DNN mappings (dataflows and tiling).☆247Apr 15, 2024Updated last year
- Next generation CGRA generator☆118Feb 14, 2026Updated 2 weeks ago
- Simulator for BitFusion☆101Aug 6, 2020Updated 5 years ago
- ☆224Oct 24, 2025Updated 4 months ago
- A simulation framework for modeling efficiency of Graph Neural Network Dataflows☆23Feb 14, 2025Updated last year