cwfletcher / buffetsLinks
Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
☆71Updated 6 years ago
Alternatives and similar repositories for buffets
Users that are interested in buffets are comparing it to the libraries listed below
Sorting:
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆91Updated 8 months ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆53Updated last month
- RTL implementation of Flex-DPE.☆100Updated 5 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆122Updated 5 years ago
- ☆52Updated 2 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 10 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆59Updated 7 months ago
- An Open-Source Tool for CGRA Accelerators☆65Updated last month
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆67Updated 11 months ago
- ☆91Updated last year
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆26Updated 8 months ago
- ☆29Updated 6 months ago
- ☆71Updated 2 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆53Updated 2 months ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago
- ☆30Updated 2 months ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆170Updated this week
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated last month
- ☆59Updated last week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆129Updated last week
- ☆86Updated last year
- EQueue Dialect☆40Updated 3 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆52Updated 2 months ago
- ☆25Updated 3 years ago