Alternatives and similar repositories for buffets:

Users that are interested in buffets are comparing it to the libraries listed below

• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆121Updated 5 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 3 years ago
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆79Updated last year
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆79Updated 6 years ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆64Updated 2 weeks ago
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆121Updated 2 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆50Updated last month
• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆65Updated last year
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆64Updated 10 months ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆90Updated 7 months ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆58Updated 6 months ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆79Updated 9 months ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆126Updated last week
• CMU-SAFARI / VAMPIRE
  An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …
  ☆38Updated 6 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆76Updated 3 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆51Updated last week
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆99Updated 5 years ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆30Updated 3 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆91Updated last year
• cucapra / EventQueue
  EQueue Dialect
  ☆40Updated 3 years ago
• GT-CHIPS / gem5_chips
  gem5 repository to study chiplet-based systems
  ☆72Updated 6 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆88Updated last month
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆56Updated 3 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆51Updated last month
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆29Updated 2 weeks ago
• StanfordAHA / aha
  ☆58Updated this week
• pnnl / soda-opt
  ☆44Updated last month
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆49Updated last month
• hngenc / stellar
  ☆27Updated 6 months ago