cwfletcher / buffetsLinks
Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
☆72Updated 6 years ago
Alternatives and similar repositories for buffets
Users that are interested in buffets are comparing it to the libraries listed below
Sorting:
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆92Updated 8 months ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆81Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆124Updated 5 years ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated 11 months ago
- ☆24Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆54Updated this week
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆59Updated 8 months ago
- Release of stream-specialization software/hardware stack.☆122Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆67Updated 2 months ago
- ☆55Updated 3 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 10 months ago
- ☆30Updated 7 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆132Updated last week
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆54Updated 3 months ago
- CGRA framework with vectorization support.☆32Updated this week
- RTL implementation of Flex-DPE.☆103Updated 5 years ago
- ☆59Updated this week
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆37Updated 2 years ago
- CGRA Compilation Framework☆84Updated last year
- ☆91Updated last year
- ☆71Updated 2 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆73Updated 2 weeks ago
- Processing in Memory Emulation☆20Updated 2 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 3 months ago