Accelergy-Project / timeloop-accelergy-exercisesLinks
Exercises for exploring the Fibertree, Timeloop and Accelergy tools
☆113Updated 9 months ago
Alternatives and similar repositories for timeloop-accelergy-exercises
Users that are interested in timeloop-accelergy-exercises are comparing it to the libraries listed below
Sorting:
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆154Updated 8 months ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆62Updated 3 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆74Updated 3 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Updated 4 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 6 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Updated 6 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated last week
- STONNE: A Simulation Tool for Neural Networks Engines☆145Updated 7 months ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆180Updated last week
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆71Updated 4 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆84Updated 4 years ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆114Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆85Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Updated 11 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆70Updated last month
- MICRO22 artifact evaluation for Sparseloop☆47Updated 3 years ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆68Updated 2 years ago
- ☆62Updated 10 months ago
- ☆42Updated last year
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆75Updated 2 years ago
- ☆72Updated 2 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆74Updated last year
- Automatic generation of FPGA-based learning accelerators for the neural network family☆68Updated 6 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆43Updated 2 years ago
- ☆35Updated 5 years ago
- ☆71Updated 5 years ago