Accelergy-Project / timeloop-accelergy-exercises
Exercises for exploring the Fibertree, Timeloop and Accelergy tools
☆89Updated last month
Alternatives and similar repositories for timeloop-accelergy-exercises:
Users that are interested in timeloop-accelergy-exercises are comparing it to the libraries listed below
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆60Updated 3 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆47Updated this week
- MICRO22 artifact evaluation for Sparseloop☆41Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆75Updated 5 months ago
- RTL implementation of Flex-DPE.☆97Updated 4 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆132Updated last month
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆43Updated 3 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆35Updated last year
- Docker container with tools for the Timeloop/Accelergy tutorial☆22Updated 9 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆46Updated this week
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆66Updated 5 years ago
- ☆69Updated 4 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆77Updated last year
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆125Updated this week
- The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …☆118Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆67Updated 3 years ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆123Updated this week
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆26Updated 6 years ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆61Updated last year
- ☆71Updated last year
- Tool for optimize CNN blocking☆93Updated 4 years ago
- ☆37Updated 6 months ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆83Updated last month
- STONNE: A Simulation Tool for Neural Networks Engines☆123Updated 7 months ago
- Approximate layers - TensorFlow extension☆26Updated 8 months ago
- A co-design architecture on sparse attention☆48Updated 3 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆38Updated last week
- gem5 repository to study chiplet-based systems☆69Updated 5 years ago
- An Open-Source Tool for CGRA Accelerators☆58Updated last week
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆84Updated 3 months ago