Accelergy-Project / timeloop-accelergy-exercisesLinks
Exercises for exploring the Fibertree, Timeloop and Accelergy tools
☆101Updated 3 months ago
Alternatives and similar repositories for timeloop-accelergy-exercises
Users that are interested in timeloop-accelergy-exercises are comparing it to the libraries listed below
Sorting:
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆56Updated 4 months ago
- RTL implementation of Flex-DPE.☆108Updated 5 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆147Updated 2 months ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆56Updated 3 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆148Updated this week
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆94Updated 10 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated last year
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆154Updated last week
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆57Updated last month
- STONNE: A Simulation Tool for Neural Networks Engines☆135Updated last month
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆72Updated last year
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆65Updated 2 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆60Updated 4 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆82Updated last year
- ☆71Updated 5 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆76Updated 6 years ago
- ☆41Updated last year
- MICRO22 artifact evaluation for Sparseloop☆44Updated 2 years ago
- ☆64Updated last month
- ☆35Updated 5 years ago
- ☆72Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 5 months ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆67Updated 5 years ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆111Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆67Updated 3 months ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆32Updated this week
- Eyeriss chip simulator☆36Updated 5 years ago