Accelergy-Project / processing-in-memory-designLinks
☆25Updated last year
Alternatives and similar repositories for processing-in-memory-design
Users that are interested in processing-in-memory-design are comparing it to the libraries listed below
Sorting:
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆19Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆84Updated last year
- ☆40Updated last year
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Updated 2 years ago
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆28Updated last year
- ACM TODAES Best Paper Award, 2022☆28Updated last year
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆57Updated 5 months ago
- STONNE Simulator integrated into SST Simulator☆21Updated last year
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆67Updated 2 years ago
- NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators☆21Updated 6 months ago
- Heterogenous ML accelerator☆19Updated 4 months ago
- A general framework for optimizing DNN dataflow on systolic array☆39Updated 4 years ago
- Processing in Memory Emulation☆22Updated 2 years ago
- ☆33Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 7 months ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆56Updated 4 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆72Updated last year
- ☆29Updated 3 years ago
- Docker container with tools for the Timeloop/Accelergy tutorial☆22Updated last year
- ☆72Updated 2 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- Fibertree emulator☆14Updated 11 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago