HewlettPackard / cacti
An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model
☆421Updated 6 months ago
Alternatives and similar repositories for cacti:
Users that are interested in cacti are comparing it to the libraries listed below
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆335Updated 5 months ago
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆176Updated 4 years ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆227Updated 2 years ago
- A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, …☆606Updated last year
- DRAMSim2: A cycle accurate DRAM simulator☆260Updated 4 years ago
- Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …☆272Updated last month
- BookSim 2.0☆294Updated 6 months ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆237Updated 2 months ago
- Repository to host and maintain scale-sim-v2 code☆255Updated last week
- A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combi…☆151Updated 2 years ago
- PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.☆191Updated last year
- Network on Chip Simulator☆253Updated 11 months ago
- Fast and accurate DRAM power and energy estimation tool☆144Updated this week
- AutoSA: Polyhedral-Based Systolic Array Compiler☆207Updated 2 years ago
- A pre-RTL, power-performance model for fixed-function accelerators☆173Updated last year
- ☆340Updated last year
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆391Updated this week
- A scalable High-Level Synthesis framework on MLIR☆239Updated 8 months ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆266Updated 2 months ago
- Learning gem5 is a work-in-progress book to help gem5 users get started using gem5.☆178Updated 2 years ago
- Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.☆357Updated 3 weeks ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆351Updated this week
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆316Updated 2 years ago
- This is the top-level repository for the Accel-Sim framework.☆327Updated 2 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆137Updated last year
- Berkeley's Spatial Array Generator☆855Updated last month
- STONNE: A Simulation Tool for Neural Networks Engines☆123Updated 7 months ago
- Modeling Architectural Platform☆175Updated this week
- An analytical cost model evaluating DNN mappings (dataflows and tiling).☆198Updated 9 months ago
- ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture …☆544Updated last week