AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog
☆19Sep 2, 2023Updated 2 years ago
Alternatives and similar repositories for AMBA
Users that are interested in AMBA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- AHB Bus lite v3.0☆17Aug 7, 2019Updated 6 years ago
- General Purpose IO with APB4 interface☆16May 10, 2024Updated last year
- APB Timer Unit☆14Oct 30, 2025Updated 6 months ago
- FPGA Low latency 10GBASE-R PCS☆13May 23, 2023Updated 2 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- AXI4 with a FIFO integrated with VIP☆24Feb 29, 2024Updated 2 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- Test Realtime FIR/IIR Filter using FMAC (Filter Math ACCcelerator). The FMAC unit is built around a fixed point multiplier and accumulato…☆13Nov 10, 2021Updated 4 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆35Mar 21, 2020Updated 6 years ago
- ☆20Nov 18, 2022Updated 3 years ago
- UART implementation using verilog☆36Feb 14, 2023Updated 3 years ago
- ☆14Jul 5, 2019Updated 6 years ago
- Interface Protocol in Verilog☆51Aug 2, 2019Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆17Oct 6, 2024Updated last year
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆14Jul 28, 2021Updated 4 years ago
- APB Logic☆26Feb 24, 2026Updated 2 months ago
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆27Sep 8, 2024Updated last year
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Dec 23, 2022Updated 3 years ago
- UVM Testbench for synchronus fifo☆19Aug 28, 2020Updated 5 years ago
- ☆15Updated this week
- A verilog based 5-stage pipelined RISC-V Processor code.☆37Mar 25, 2020Updated 6 years ago
- ☆27Jun 26, 2014Updated 11 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Universal Advanced JTAG Debug Interface☆17May 10, 2024Updated last year
- ☆18Apr 5, 2015Updated 11 years ago
- RISC-V soft-core PEs for TaPaSCo☆23Jan 30, 2026Updated 3 months ago
- Repository for keeping code from YouTube Tutorials☆11Sep 27, 2022Updated 3 years ago
- To design test bench of the APB protocol☆20Dec 30, 2020Updated 5 years ago
- Asynchronous fifo in verilog☆38Mar 20, 2016Updated 10 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- ☆14Jun 22, 2022Updated 3 years ago
- ☆16Jul 1, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆26Jan 1, 2022Updated 4 years ago
- Open source tools for IC design☆13Dec 12, 2024Updated last year
- Source-Opened RISCV for Crypto☆18Jan 18, 2022Updated 4 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆18Oct 19, 2024Updated last year
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Jan 17, 2026Updated 3 months ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago