racosa / cnn-accelerator
A Convolutional Neural Network (CNN) hardware accelerator for image recognition
☆13Updated 5 years ago
Alternatives and similar repositories for cnn-accelerator:
Users that are interested in cnn-accelerator are comparing it to the libraries listed below
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- ☆26Updated 5 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆43Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 5 years ago
- tpu-systolic-array-weight-stationary☆24Updated 3 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆14Updated 4 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆63Updated 2 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆98Updated 4 years ago
- ☆63Updated 6 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- ☆31Updated 5 years ago
- Verilog implementation of Softmax function☆64Updated 2 years ago
- DMA controller for CNN accelerator☆13Updated 7 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- ☆3Updated 3 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- The Verilog source code for DRUM approximate multiplier.☆30Updated last year
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 3 years ago
- A collection of tutorials for the fpgaConvNet framework.☆39Updated 7 months ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆71Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆155Updated 5 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆32Updated last year
- Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).☆21Updated 6 years ago