A Convolutional Neural Network (CNN) hardware accelerator for image recognition
☆15Jul 14, 2019Updated 7 years ago
Alternatives and similar repositories for cnn-accelerator
Users that are interested in cnn-accelerator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository contains source code for CNN layers of ALexNet using Xilinx HLS Vivado.☆10Jun 25, 2022Updated 4 years ago
- test images with not appropriate labels in MNIST dataset☆10Mar 3, 2018Updated 8 years ago
- FPGA-based HyperLogLog Accelerator☆12Jul 13, 2020Updated 6 years ago
- This repository contains all the materials related to the basic MOSFET theory, CMOS technology, circuit and layout design, and basic PDK …☆15Dec 15, 2023Updated 2 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- Opportunistic Protocol Simulator☆15Oct 17, 2023Updated 2 years ago
- ☆15Feb 6, 2021Updated 5 years ago
- This is a Project to Integrate and Automate the functions of three tools named gem5, McPAT and HotSpot.☆11Jul 1, 2019Updated 7 years ago
- The CNN architecture elements implemented with RTL approach in VHDL.☆16May 9, 2019Updated 7 years ago
- 银行基本业务系统后端实现☆10Nov 9, 2018Updated 7 years ago
- Hardware accelerator for convolutional neural networks☆76Aug 9, 2022Updated 3 years ago
- ☆41Feb 28, 2022Updated 4 years ago
- Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Syno…☆14Jun 9, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆20Dec 3, 2019Updated 6 years ago
- Example of a full DC synthesis script for a simple design☆14Feb 25, 2019Updated 7 years ago
- ☆15Dec 2, 2021Updated 4 years ago
- IEEE Executive project for the year 2021-2022☆11Nov 22, 2022Updated 3 years ago
- ☆14May 14, 2024Updated 2 years ago
- ☆35Mar 1, 2019Updated 7 years ago
- A crypto accelerator written for HLS to an FPGA that actually makes it slower than running it on your computer☆19Dec 11, 2018Updated 7 years ago
- ☆12Nov 28, 2024Updated last year
- This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2☆17Jan 27, 2018Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆14Dec 10, 2022Updated 3 years ago
- Some beginner projects using verilog HDL, along with some documentation on basic syntax☆14Jun 13, 2021Updated 5 years ago
- A modified version of McPAT for the COSSIM framework. The code is based on McPAT v1.3 and integrates with cgem5.☆18Mar 21, 2022Updated 4 years ago
- ☆17Mar 9, 2026Updated 4 months ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆17Oct 16, 2021Updated 4 years ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆16Sep 28, 2017Updated 8 years ago
- ☆18Dec 13, 2022Updated 3 years ago
- A pipelined brainfuck softcore in Verilog☆20Aug 5, 2014Updated 11 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆52May 20, 2026Updated 2 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.☆82Oct 3, 2023Updated 2 years ago
- YOLOv3 C++☆17Jan 4, 2020Updated 6 years ago
- ☆23Jul 20, 2023Updated 3 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆20May 29, 2018Updated 8 years ago
- Reconfigurable Binary Engine☆18Mar 23, 2021Updated 5 years ago
- Simple SAT solver with CDCL implemented in Python☆19Jan 5, 2023Updated 3 years ago
- GNU toolchain for PULP and RISC-V☆14Mar 15, 2025Updated last year