Alternatives and similar repositories for cnn-accelerator

Users that are interested in cnn-accelerator are comparing it to the libraries listed below

• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆48Updated 5 years ago
• eda-lab / CNNAF-CNN-Accelerator
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆10Updated 3 years ago
• 0x5b25 / CNN_Core
  A CNN accelerator design inspired by MIT Eyeriss project
  ☆20Updated 4 years ago
• ChrisZonghaoLi / cnn_conv_accelerator
  A Fix-pointed Rudimentary CNN Convolution Accelerator
  ☆16Updated 5 years ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆73Updated 3 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆57Updated 3 years ago
• haroonrl / DNN_HLS_Accelerator
  This repository contains source code for CNN layers of ALexNet using Xilinx HLS Vivado.
  ☆10Updated 3 years ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆46Updated last year
• SivannaKing / SEU-ASIC-IOT-ECGAI
  Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators
  ☆16Updated 2 years ago
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆12Updated 5 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆54Updated 4 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆17Updated 4 years ago
• lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS
  This project implements a convolution kernel based on vivado HLS on zcu104
  ☆37Updated 5 years ago
• yayouz / CNN-accelerator
  DMA controller for CNN accelerator
  ☆14Updated 8 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆70Updated 6 years ago
• kuladeepsaireddy / OpenNoc
  ☆37Updated 6 years ago
• louislxw / pe_array
  A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…
  ☆13Updated last year
• nimish15shah / DPU_DAG_Processing_Unit
  RTL code for the DPU chip designed for irregular graphs
  ☆13Updated 3 years ago
• ralbertazzi / bnn
  Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools
  ☆52Updated 7 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆59Updated 3 years ago
• ZhangYuQAQ / Hardware-Acceleration-Circuit-Design-of-Object-Detection-Network-Based-on-FPGA
  2020 xilinx summer school
  ☆18Updated 5 years ago
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆41Updated 2 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆104Updated 5 years ago
• awai54st / LUTNet
  ☆60Updated 5 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆173Updated 5 years ago
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆45Updated last year
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆36Updated 3 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆49Updated 7 years ago
• neasotho / SystolicArray_FPGA
  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
  ☆13Updated 5 years ago
• ehw-fit / evoapproxlib
  Library of approximate arithmetic circuits
  ☆56Updated 3 years ago