Alternatives and similar repositories for CNN-on-FPGA:

Users that are interested in CNN-on-FPGA are comparing it to the libraries listed below

• snagiri / CSE237D-PYNQ-SNN-Accelerator
  Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board
  ☆36Updated 5 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆24Updated 3 years ago
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆11Updated 4 years ago
• djtfoo / lenet5-verilog
  A Verilog design of LeNet-5, a Convolutional Neural Network architecture
  ☆30Updated 4 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆16Updated 3 years ago
• saunak1994 / CyNAPSEv11
  The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL
  ☆33Updated 5 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆43Updated 2 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆50Updated 3 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆30Updated 4 years ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆39Updated 7 months ago
• ahirsharan / LSTM
  Single Long Short Term Memory (LSTM) cell : Verilog Implementation
  ☆30Updated 4 years ago
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆32Updated last year
• arkhodamoradi / s2n2
  ☆17Updated 4 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆65Updated 2 months ago
• jonathan93sh / CNNA
  A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA
  ☆23Updated 3 years ago
• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆47Updated 5 years ago
• FSq-Poplar / FPGA_NN
  A neural network built in Verilog for the DE1-SoC FPGA board for handwritten digit recognition.
  ☆17Updated 5 years ago
• eda-lab / CNNAF-CNN-Accelerator
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆10Updated 3 years ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆30Updated 2 years ago
• ankitgarg1999 / COP-820
  Eyeriss Hardware Accelerator for Machine Learning
  ☆10Updated 2 years ago
• stellagarden / EE405-Advanced-Digital-Systems-Design
  Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator
  ☆8Updated last year
• SivannaKing / SEU-ASIC-IOT-ECGAI
  Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators
  ☆17Updated last year
• oshears / SNN-FPGA-Implementation
  ☆18Updated 4 years ago
• bol-edu / 2022-fall-ntu
  ☆32Updated 7 months ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆63Updated 6 years ago
• JinChen-tw / pynqz2_dpu140
  This TRD is implement DPU v1.4.0 on PYNQ-Z2 board
  ☆44Updated 4 years ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆27Updated 6 years ago
• jerry-D / HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine
  HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…
  ☆58Updated last month
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆12Updated 5 years ago