trung-pham-dinh / CNN-on-FPGA
☆16Updated 2 years ago
Alternatives and similar repositories for CNN-on-FPGA:
Users that are interested in CNN-on-FPGA are comparing it to the libraries listed below
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 5 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆28Updated 4 years ago
- A neural network built in Verilog for the DE1-SoC FPGA board for handwritten digit recognition.☆15Updated 5 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆29Updated 2 years ago
- tpu-systolic-array-weight-stationary☆23Updated 3 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆31Updated last year
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 4 years ago
- ☆63Updated 6 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆91Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆55Updated last month
- Hardware accelerator for convolutional neural networks☆40Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- A collection of tutorials for the fpgaConvNet framework.☆41Updated 6 months ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆33Updated 5 years ago
- ☆16Updated 3 years ago
- An LeNet RTL implement onto FPGA☆44Updated 6 years ago
- ☆104Updated 4 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆9Updated 3 years ago
- Single Long Short Term Memory (LSTM) cell : Verilog Implementation☆30Updated 4 years ago
- Eyeriss Hardware Accelerator for Machine Learning☆9Updated 2 years ago
- Open-source of MSD framework☆16Updated last year
- A Spiking Neuron Network Project in Verilog Implementation☆21Updated 6 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆147Updated 5 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆29Updated 4 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆58Updated 3 weeks ago
- ☆17Updated 4 years ago