Reconfigurable Binary Engine
☆17Mar 23, 2021Updated 4 years ago
Alternatives and similar repositories for rbe
Users that are interested in rbe are comparing it to the libraries listed below
Sorting:
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV☆12Mar 9, 2026Updated last week
- ☆35Mar 8, 2023Updated 3 years ago
- An example Hardware Processing Engine☆12Feb 4, 2023Updated 3 years ago
- A Barrel design of RV32I☆22Jul 30, 2023Updated 2 years ago
- ☆17Dec 21, 2020Updated 5 years ago
- Neural Engine, 16 input channels☆16Oct 31, 2022Updated 3 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆22Mar 25, 2025Updated 11 months ago
- ☆13May 10, 2018Updated 7 years ago
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- This repo is for Edge Vision SoC framework, which facilitates quick porting of users' design for Edge AI and Vision solutions.☆26Feb 13, 2026Updated last month
- A tool to deploy Deep Neural Networks on PULP-based SoC's☆93Aug 4, 2025Updated 7 months ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated 3 weeks ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆94Jan 5, 2025Updated last year
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- ☆10Nov 2, 2023Updated 2 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- Scalable In-Memory Acceleration With Mesh: Device, Circuits, Architecture, and Algorithm☆16Oct 11, 2020Updated 5 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆32Mar 4, 2026Updated 2 weeks ago
- ☆13May 14, 2024Updated last year
- Some materials and sample source for RV32 OS projects.☆22May 31, 2022Updated 3 years ago
- ☆12Nov 28, 2024Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Sep 24, 2021Updated 4 years ago
- RISC-V Core Local Interrupt Controller (CLINT)☆30Mar 10, 2026Updated last week
- ☆14Dec 10, 2022Updated 3 years ago
- Bluespec environment for working with the ulx3s board and its lattice ecp5 fpga☆15Mar 9, 2025Updated last year
- A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.☆15Jan 14, 2022Updated 4 years ago
- Filter builder tool☆18Apr 11, 2022Updated 3 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆13May 14, 2019Updated 6 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Aug 28, 2023Updated 2 years ago
- Contains commonly used UVM components (agents, environments and tests).☆32Aug 17, 2018Updated 7 years ago
- Video Effects on VGA☆15Jan 7, 2019Updated 7 years ago
- A vector graphics renderer for bgfx, based on ideas from NanoVG and ImDrawList (Dear ImGUI)☆10Feb 11, 2026Updated last month
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 4 years ago
- SPIR-V fragment shader GPU core based on RISC-V☆44May 26, 2021Updated 4 years ago
- ucas hpc course code☆15May 24, 2023Updated 2 years ago
- Toy RISC-V emulator☆15Oct 10, 2017Updated 8 years ago
- Stencil with Optimized Dataflow Architecture☆18Feb 27, 2024Updated 2 years ago