Basantloay / Softmax_CNNLinks
This repository contains full code of Softmax Layer in Verilog
☆18Updated 5 years ago
Alternatives and similar repositories for Softmax_CNN
Users that are interested in Softmax_CNN are comparing it to the libraries listed below
Sorting:
- Systolic array based simple TPU for CNN on PYNQ-Z2☆36Updated 3 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆41Updated 2 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆57Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆17Updated 4 years ago
- This project is to design yolo AI accelerator in verilog HDL.☆28Updated last year
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆13Updated 4 years ago
- Verilog implementation of Softmax function☆70Updated 3 years ago
- ☆36Updated 6 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆112Updated 2 months ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆28Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆172Updated 5 years ago
- ☆119Updated 5 years ago
- 使用FPGA实现CNN模型☆15Updated 6 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆68Updated last year
- verilog实现TPU中的脉动阵列计算卷积的module☆132Updated 5 months ago
- Convolutional Neural Network Using High Level Synthesis☆88Updated 5 years ago
- ☆68Updated 6 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆38Updated 6 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆20Updated 4 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆35Updated 5 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆60Updated 4 years ago
- A systolic array matrix multiplier☆25Updated 6 years ago
- 3×3脉动阵列乘法器☆46Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- ☆42Updated 4 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆25Updated 7 years ago