Basantloay / Softmax_CNNLinks
This repository contains full code of Softmax Layer in Verilog
☆20Updated 5 years ago
Alternatives and similar repositories for Softmax_CNN
Users that are interested in Softmax_CNN are comparing it to the libraries listed below
Sorting:
- Systolic array based simple TPU for CNN on PYNQ-Z2☆40Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- Hardware accelerator for convolutional neural networks☆60Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- This project is to design yolo AI accelerator in verilog HDL.☆28Updated last year
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆41Updated 2 years ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- Verilog implementation of Softmax function☆78Updated 3 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆123Updated 5 months ago
- ☆123Updated 5 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆16Updated 4 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆37Updated last year
- verilog实现TPU中的脉动阵列计算卷积的module☆148Updated 7 months ago
- ☆71Updated 7 years ago
- ☆45Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆177Updated 6 years ago
- ☆40Updated 6 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆112Updated 5 years ago
- A systolic array matrix multiplier☆30Updated 6 years ago
- ☆14Updated 2 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆13Updated last year
- A DNN Accelerator implemented with RTL.☆68Updated 11 months ago
- Convolutional accelerator kernel, target ASIC & FPGA☆237Updated 2 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Updated 4 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆39Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- 使用FPGA实现CNN模型☆15Updated 6 years ago