Basantloay / Softmax_CNN
This repository contains full code of Softmax Layer in Verilog
☆16Updated 4 years ago
Alternatives and similar repositories for Softmax_CNN:
Users that are interested in Softmax_CNN are comparing it to the libraries listed below
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆26Updated last year
- Verilog implementation of Softmax function☆54Updated 2 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆13Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆33Updated 2 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆25Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆39Updated 4 months ago
- verilog实现TPU中的脉动阵列计算卷积的module☆72Updated 3 years ago
- ☆26Updated 5 years ago
- ☆14Updated last year
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆32Updated 5 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆10Updated 3 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆42Updated 4 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆14Updated 5 years ago
- 3×3脉动阵列乘法器☆36Updated 5 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 3 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆21Updated 2 years ago
- ☆98Updated 4 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆32Updated 3 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆27Updated 4 years ago
- DMA controller for CNN accelerator☆13Updated 7 years ago
- 使用FPGA实现CNN模型☆13Updated 5 years ago
- ☆9Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆135Updated 5 years ago
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆12Updated last year
- CNN accelerator using NoC architecture☆15Updated 6 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆23Updated 4 years ago
- An LeNet RTL implement onto FPGA☆40Updated 6 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆33Updated 5 months ago