Basantloay / Softmax_CNNLinks
This repository contains full code of Softmax Layer in Verilog
☆21Updated 5 years ago
Alternatives and similar repositories for Softmax_CNN
Users that are interested in Softmax_CNN are comparing it to the libraries listed below
Sorting:
- Verilog implementation of Softmax function☆78Updated 3 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆41Updated 3 years ago
- Hardware accelerator for convolutional neural networks☆65Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- This project is to design yolo AI accelerator in verilog HDL.☆31Updated last year
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆43Updated 2 years ago
- A systolic array matrix multiplier☆30Updated 6 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- ☆40Updated 6 years ago
- ☆124Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆115Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆133Updated 6 months ago
- ☆47Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆180Updated 6 years ago
- ☆73Updated 7 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆156Updated 8 months ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆13Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆71Updated last year
- Tensor Processing Unit implementation in Verilog☆13Updated 10 months ago
- Verilog Implementation of 32-bit Floating Point Adder☆46Updated 5 years ago
- A verilog implementation for Network-on-Chip☆81Updated 8 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆16Updated 4 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆77Updated 5 years ago
- 使用FPGA实现CNN模型☆15Updated 6 years ago
- 3×3脉动阵列乘法器☆50Updated 6 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆242Updated 2 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago