This repository contains full code of Softmax Layer in Verilog
☆21Jul 29, 2020Updated 5 years ago
Alternatives and similar repositories for Softmax_CNN
Users that are interested in Softmax_CNN are comparing it to the libraries listed below
Sorting:
- Verilog implementation of Softmax function☆80Jul 27, 2022Updated 3 years ago
- Hardware accelerator for convolutional neural networks☆67Aug 9, 2022Updated 3 years ago
- This repository implements a scaled-down LLaMA 2-like model on an ARM Cortex-M3 soft core, with a custom systolic array RTL module for ef…☆13Jun 25, 2025Updated 8 months ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Apr 18, 2019Updated 6 years ago
- An FPGA design for simulating biological neurons☆17Jul 5, 2024Updated last year
- RTL code for the DPU chip designed for irregular graphs☆13May 30, 2022Updated 3 years ago
- bitfusion verilog implementation☆12Feb 21, 2022Updated 4 years ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- A convolutional neural network implemented in hardware (verilog)☆166Sep 7, 2017Updated 8 years ago
- Converting a deep neural network to integer-only inference in native C via uniform quantization and the fixed-point representation.☆25Jan 31, 2022Updated 4 years ago
- ☆14Mar 22, 2024Updated 2 years ago
- Fixed point math library for SystemVerilog☆42Nov 14, 2024Updated last year
- This is a verilog implementation of 4x4 systolic array multiplier☆80Nov 2, 2020Updated 5 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆18Feb 12, 2024Updated 2 years ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated last year
- A project implementing the CORDIC algorithm for computing cosines and sines using fixed-point decimals in Verilog code（使用定点小数在 verilog 代码…☆11Aug 19, 2023Updated 2 years ago
- Recent works have demonstrated that deep learning algorithms were very efficient to conduct security evaluations of embedded systems and …☆14Mar 13, 2019Updated 7 years ago
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆29Feb 21, 2024Updated 2 years ago
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 4 years ago
- Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determine…☆15Jun 15, 2016Updated 9 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Jan 4, 2018Updated 8 years ago
- Hardware and software implementation of Sparsely-active SNNs☆22Mar 6, 2026Updated 2 weeks ago
- Implementation of CNN using Verilog☆244Oct 13, 2017Updated 8 years ago
- A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.☆17May 30, 2023Updated 2 years ago
- Convolutional Neural Network RTL-level Design☆77Oct 22, 2021Updated 4 years ago
- LLMA = LLM + Arithmetic coder, which use LLM to do insane text data compression. LLMA=大模型+算术编码，它能使用LLM对文本数据进行暴力的压缩，达到极高的压缩率。☆22Nov 24, 2024Updated last year
- Deep Learning Accelerator (Convolution Neural Networks)☆199Dec 15, 2017Updated 8 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 4 years ago
- ☆18May 5, 2022Updated 3 years ago
- ☆28Feb 5, 2020Updated 6 years ago
- A vision transformer based framework for classifying executable images as benign or malicious☆10Mar 19, 2024Updated 2 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆77Dec 30, 2019Updated 6 years ago
- Getting started with RISC-V☆14Jun 4, 2023Updated 2 years ago
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- RISC-V RV32E core designed for minimal area☆26Nov 17, 2024Updated last year
- Verilog FPGA code : including experimental DSP audio processor☆13Dec 1, 2020Updated 5 years ago
- Open hardware & software DIY spin coater☆19Dec 2, 2025Updated 3 months ago