Alternatives and similar repositories for Verilog-Practice:

Users that are interested in Verilog-Practice are comparing it to the libraries listed below

• viduraakalanka / HDL-Bits-Solutions
  This is a repository containing solutions to the problem statements given in HDL Bits website.
  ☆343Updated last year
• sin-x / FPGA
  数字IC相关资料
  ☆1,067Updated 4 years ago
• pConst / basic_verilog
  Must-have verilog systemverilog modules
  ☆1,716Updated 3 months ago
• openFPGA666 / FpgaGuide
  分享FPGA开发知识、优秀文章、学习网站以及开源项目。本项目收集了github中许多FPGA开源项目。
  ☆500Updated last year
• WangXuan95 / Xilinx-FPGA-PCIe-XDMA-Tutorial
  Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
  ☆526Updated last year
• Nitcloud / Digital-IDE
  在vscode上的数字设计开发插件
  ☆350Updated 2 years ago
• dumpo / digital_IC_design_notes
  数字IC设计 学习笔记
  ☆128Updated 3 years ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,609Updated last year
• omarelhedaby / CNN-FPGA
  Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database
  ☆449Updated 4 years ago
• suisuisi / FPGAandCNN
  基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现
  ☆294Updated last year
• QShen3 / CNN-FPGA
  使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用
  ☆522Updated 6 years ago
• xupsh / pp4fpgas-cn
  中文版 Parallel Programming for FPGAs
  ☆718Updated 6 months ago
• xupsh / Digital-Design-Lab
  ☆213Updated 3 years ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆403Updated 5 years ago
• Xilinx / Vitis-HLS-Introductory-Examples
  ☆642Updated 3 months ago
• WalkerLau / DetectHumanFaces
  Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
  ☆195Updated last year
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆139Updated 2 months ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆743Updated 3 years ago
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,211Updated 9 months ago
• sudhamshu091 / 32-Verilog-Mini-Projects
  Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …
  ☆621Updated 3 months ago
• suisuisi / FPGA_Library
  Vivado诸多IP，包括图像处理等
  ☆191Updated 6 months ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆576Updated 7 months ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,404Updated 4 months ago
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆77Updated 3 years ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆777Updated 6 months ago
• doonny / basic_knowledge
  Things to learn for new students in the Lab for AI chips and systems of BJTU .
  ☆184Updated 3 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,204Updated 3 weeks ago
• cxlisme / FPGA-proj
  FPGA project
  ☆206Updated 2 years ago
• HonkW93 / automatic-verilog
  automatic-verilog based on vimscript
  ☆250Updated last year
• KastnerRG / riffa
  The RIFFA development repository
  ☆800Updated 8 months ago