HDLBits website practices & solutions
☆812Dec 27, 2023Updated 2 years ago
Alternatives and similar repositories for Verilog-Practice
Users that are interested in Verilog-Practice are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目☆5,756May 15, 2022Updated 4 years ago
- Must-have verilog systemverilog modules☆2,020Mar 12, 2026Updated 6 months ago
- This is a repository containing solutions to the problem statements given in HDL Bits website.☆379Jul 16, 2023Updated 3 years ago
- 数字IC相关资料☆1,619Jul 1, 2025Updated last year
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆21Aug 6, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,854Mar 24, 2021Updated 5 years ago
- Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).☆93Sep 20, 2023Updated 3 years ago
- AMBA bus lecture material☆554Jan 21, 2020Updated 6 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆630Mar 15, 2018Updated 8 years ago
- Verilog library for ASIC and FPGA designers☆1,442May 8, 2024Updated 2 years ago
- Verilog AXI components for FPGA implementation☆2,143Feb 27, 2025Updated last year
- Learn how to design digital systems and synthesize them into an FPGA using only opensource tools☆871Apr 15, 2020Updated 6 years ago
- All About HDL☆40Aug 21, 2019Updated 7 years ago
- ☆235Mar 21, 2021Updated 5 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- The Ultra-Low Power RISC-V Core☆1,923Aug 6, 2025Updated last year
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆243Apr 12, 2021Updated 5 years ago
- 中文版 Parallel Programming for FPGAs☆773Aug 21, 2024Updated 2 years ago
- HDL libraries and projects☆2,017Updated this week
- IC design and development should be faster，simpler and more reliable☆2,020Dec 31, 2021Updated 4 years ago
- A very simple and easy to understand RISC-V core.☆1,533Nov 9, 2023Updated 2 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, op…☆112Sep 17, 2022Updated 4 years ago
- Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。☆169Jan 20, 2019Updated 7 years ago
- Verilog Ethernet components for FPGA implementation☆3,102Feb 27, 2025Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆11Nov 24, 2020Updated 5 years ago
- This is a practice of verilog coding☆33Jul 10, 2019Updated 7 years ago
- 一步一步写MIPS CPU☆882Jun 5, 2026Updated 3 months ago
- ☆146Oct 3, 2020Updated 5 years ago
- Various HDL (Verilog) IP Cores☆934Jul 1, 2021Updated 5 years ago
- Verification of an Asynchronous FIFO using UVM & SVA☆13Jun 26, 2025Updated last year
- 一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。☆612Sep 15, 2023Updated 3 years ago
- 分享FPGA开发知识、优秀文章、学习网站以及开源项目。本项目收集了github中许多FPGA开源项目。☆867Apr 21, 2023Updated 3 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆203Jul 23, 2018Updated 8 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- training labs and examples☆472Aug 1, 2022Updated 4 years ago
- ☆154Mar 9, 2026Updated 6 months ago
- A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard☆928Jul 29, 2024Updated 2 years ago
- This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.☆794Dec 10, 2019Updated 6 years ago
- An OpenCL-based FPGA Accelerator for Convolutional Neural Networks☆1,390Feb 14, 2022Updated 4 years ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,158Updated this week
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 10 years ago