HDLBits website practices & solutions
☆778Dec 27, 2023Updated 2 years ago
Alternatives and similar repositories for Verilog-Practice
Users that are interested in Verilog-Practice are comparing it to the libraries listed below
Sorting:
- Must-have verilog systemverilog modules☆1,934Feb 19, 2026Updated 2 weeks ago
- 帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目☆5,273May 15, 2022Updated 3 years ago
- This is a repository containing solutions to the problem statements given in HDL Bits website.☆370Jul 16, 2023Updated 2 years ago
- 数字IC相关资料☆1,382Jul 1, 2025Updated 8 months ago
- Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).☆93Sep 20, 2023Updated 2 years ago
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,815Mar 24, 2021Updated 4 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆616Mar 15, 2018Updated 7 years ago
- AMBA bus lecture material☆512Jan 21, 2020Updated 6 years ago
- Verilog library for ASIC and FPGA designers☆1,392May 8, 2024Updated last year
- Learn how to design digital systems and synthesize them into an FPGA using only opensource tools☆847Apr 15, 2020Updated 5 years ago
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆241Apr 12, 2021Updated 4 years ago
- HDL libraries and projects☆1,861Updated this week
- Verilog AXI components for FPGA implementation☆1,965Feb 27, 2025Updated last year
- 中文版 Parallel Programming for FPGAs☆761Aug 21, 2024Updated last year
- The Ultra-Low Power RISC-V Core☆1,738Aug 6, 2025Updated 6 months ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, op…☆113Sep 17, 2022Updated 3 years ago
- ☆229Mar 21, 2021Updated 4 years ago
- Various HDL (Verilog) IP Cores☆876Jul 1, 2021Updated 4 years ago
- IC design and development should be faster，simpler and more reliable☆1,985Dec 31, 2021Updated 4 years ago
- All About HDL☆39Aug 21, 2019Updated 6 years ago
- ☆11Nov 24, 2020Updated 5 years ago
- ☆145Oct 3, 2020Updated 5 years ago
- Verilog Ethernet components for FPGA implementation☆2,865Feb 27, 2025Updated last year
- A very simple and easy to understand RISC-V core.☆1,396Nov 9, 2023Updated 2 years ago
- Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。☆162Jan 20, 2019Updated 7 years ago
- 一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。☆603Sep 15, 2023Updated 2 years ago
- 一步一步写MIPS CPU☆854Aug 4, 2021Updated 4 years ago
- A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard☆896Jul 29, 2024Updated last year
- training labs and examples☆449Aug 1, 2022Updated 3 years ago
- This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.☆787Dec 10, 2019Updated 6 years ago
- Verilog PCI express components☆1,541Apr 26, 2024Updated last year
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆191Jul 23, 2018Updated 7 years ago
- ☆152Dec 6, 2025Updated 2 months ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,113Sep 10, 2024Updated last year
- An OpenCL-based FPGA Accelerator for Convolutional Neural Networks☆1,368Feb 14, 2022Updated 4 years ago
- 分享FPGA开发知识、优秀文章、学习网站以及开源项目。本项目收集了github中许多FPGA开源项目。☆733Apr 21, 2023Updated 2 years ago
- 使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用☆582Jun 18, 2018Updated 7 years ago
- Vitis In-Depth Tutorials☆1,531Jan 29, 2026Updated last month
- A small, light weight, RISC CPU soft core☆1,514Dec 8, 2025Updated 2 months ago