Alternatives and similar repositories for open-fpga-verilog-tutorial

Users that are interested in open-fpga-verilog-tutorial are comparing it to the libraries listed below

• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,394Updated last year
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆570Updated 3 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆681Updated 6 months ago
• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆743Updated this week
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆613Updated 7 years ago
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,127Updated 4 months ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,384Updated this week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,340Updated this week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆1,044Updated this week
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆682Updated last month
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆460Updated last year
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,535Updated this week
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,602Updated this week
• VLSI-EDA / PoC
  The PoC Library has been forked to github.com/VHDL/PoC. See new address below
  ☆600Updated 6 months ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,745Updated 3 weeks ago
• FPGAwars / apio
  Open source ecosystem for open FPGA boards
  ☆948Updated this week
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆870Updated 4 years ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,503Updated last month
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆812Updated 3 weeks ago
• nandland / nandland
  All code found on nandland is here. underconstruction.gif
  ☆358Updated 3 years ago
• Digilent / digilent-xdc
  A collection of Master XDC files for Digilent FPGA and Zynq boards.
  ☆643Updated last year
• alexforencich / verilog-uart
  Verilog UART
  ☆532Updated 11 months ago
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆847Updated 7 months ago
• drom / awesome-hdl
  Hardware Description Languages
  ☆1,103Updated 6 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,168Updated 8 months ago
• open-logic / open-logic
  Open Logic FPGA Standard Library
  ☆855Updated last week
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆687Updated last month
• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,320Updated 3 weeks ago
• Digilent / vivado-boards
  ☆485Updated 6 months ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,248Updated this week