ljgibbslf / SM3_coreView external linksLinks
☆145Oct 3, 2020Updated 5 years ago
Alternatives and similar repositories for SM3_core
Users that are interested in SM3_core are comparing it to the libraries listed below
Sorting:
- Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-…☆30Dec 14, 2020Updated 5 years ago
- Description of Chinese SM3 Hash algorithm with Verilog HDL☆52Aug 5, 2018Updated 7 years ago
- opensource crypto IP core☆29Nov 20, 2020Updated 5 years ago
- Must-have verilog systemverilog modules☆1,926Aug 2, 2025Updated 6 months ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- ☆35Jun 9, 2022Updated 3 years ago
- IC design and development should be faster，simpler and more reliable☆1,988Dec 31, 2021Updated 4 years ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆22Oct 31, 2017Updated 8 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆110Oct 31, 2023Updated 2 years ago
- USB capture IP☆25Jun 6, 2020Updated 5 years ago
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 5 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆57Mar 11, 2018Updated 7 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Mar 17, 2022Updated 3 years ago
- RTL, Cmodel, and testbench for NVDLA☆2,023Mar 2, 2022Updated 3 years ago
- ☆31Aug 8, 2020Updated 5 years ago
- Verification IP for APB protocol☆75Dec 18, 2020Updated 5 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 4 years ago
- ☆20Jul 28, 2021Updated 4 years ago
- A MCU implementation based PODES-M0O☆19Jan 31, 2020Updated 6 years ago
- ☆20Nov 18, 2022Updated 3 years ago
- ZC RISCV CORE☆12Dec 19, 2019Updated 6 years ago
- UVM testbench for verifying the Pulpino SoC☆13Mar 23, 2020Updated 5 years ago
- Xilinx IP repository☆13May 5, 2018Updated 7 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆101Aug 9, 2024Updated last year
- ☆25Mar 25, 2019Updated 6 years ago
- Must-have verilog systemverilog modules☆37May 1, 2022Updated 3 years ago
- ☆75Jul 30, 2021Updated 4 years ago
- The RIFFA development repository☆864Jun 11, 2024Updated last year
- Verilog Model for W25Q128JVxIM Serial Flash Memory☆17Jun 7, 2020Updated 5 years ago
- Vivado诸多IP，包括图像处理等☆234Jul 28, 2024Updated last year
- ☆25Aug 11, 2021Updated 4 years ago
- OpenTitan: Open source silicon root of trust☆3,132Updated this week
- ☆16Dec 16, 2021Updated 4 years ago
- ☆220Jun 25, 2025Updated 7 months ago
- SDRAM controller with AXI4 interface☆101Aug 8, 2019Updated 6 years ago
- Deprecated, no longer updated, please change to https://www.nucleisys.com/index.php☆25Mar 24, 2021Updated 4 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- Open Source SSD Controller. NVMe and Lightstor variants☆18May 21, 2014Updated 11 years ago