Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
☆162Jan 20, 2019Updated 7 years ago
Alternatives and similar repositories for 8-bits-RISC-CPU-Verilog
Users that are interested in 8-bits-RISC-CPU-Verilog are comparing it to the libraries listed below
Sorting:
- Verilog implementation of a simple riscv cpu☆18Oct 28, 2021Updated 4 years ago
- 包括同步FIFO（输入输出位宽相同），异步FIFO（输入输出位宽相同），异步FIFO（能实现输出数据位宽是输入数据位宽的1/2或2倍）☆23Nov 7, 2022Updated 3 years ago
- Wraps the NVDLA project for Chipyard integration☆22Sep 2, 2025Updated 6 months ago
- Verilog实现的简单五级流水线CPU，开发平台：Nexys3☆40Jul 9, 2015Updated 10 years ago
- Asynchronous fifo in verilog☆38Mar 20, 2016Updated 9 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Jul 17, 2014Updated 11 years ago
- 一步一步写MIPS CPU☆854Aug 4, 2021Updated 4 years ago
- Digital Component Design course project.☆20Nov 7, 2018Updated 7 years ago
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆23Jul 20, 2023Updated 2 years ago
- x86_64 toy hypervisor☆10Nov 13, 2018Updated 7 years ago
- Verification IP for Watchdog☆12Apr 6, 2021Updated 4 years ago
- 单周期 8指令 MIPS32CPU☆96Jan 2, 2026Updated 2 months ago
- Undergraduate digital circuit laboratory☆29Jan 4, 2024Updated 2 years ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆145Jul 17, 2022Updated 3 years ago
- LeNet5 on PYNQ via HLS☆38May 29, 2023Updated 2 years ago
- 用Altera FPGA芯片自制CPU☆43Aug 10, 2014Updated 11 years ago
- ☆17Jun 19, 2021Updated 4 years ago
- a multiplier÷r verilog RTL file for RV32M instructions☆14Mar 17, 2020Updated 5 years ago
- FPGA implementation of the 8051 Microcontroller (Verilog)☆53Sep 27, 2014Updated 11 years ago
- Wishbone SATA Controller☆24Oct 16, 2025Updated 4 months ago
- Matrix multiplication accelerator on ZYNQ SoC.☆12Apr 29, 2025Updated 10 months ago
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆348Jan 12, 2018Updated 8 years ago
- HDLBits website practices & solutions☆778Dec 27, 2023Updated 2 years ago
- IOb_SoC version of the Picorv32 RISC-V Verilog IP core☆14Dec 22, 2025Updated 2 months ago
- Verilog Model for W25Q128JVxIM Serial Flash Memory☆17Jun 7, 2020Updated 5 years ago
- ZYNQ-7000 based data transfer through TCP/IP protocol☆12Apr 20, 2023Updated 2 years ago
- ASIC Design of the openSPARC Floating Point Unit☆15Mar 13, 2017Updated 8 years ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,493Jan 7, 2026Updated last month
- Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation☆294Feb 11, 2024Updated 2 years ago
- RISC-V CPU Core (RV32IM)☆1,646Sep 18, 2021Updated 4 years ago
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆196Oct 9, 2019Updated 6 years ago
- SPI通信实现FLASH读写☆16Mar 18, 2020Updated 5 years ago
- AXI-4 RAM Tester Component☆21Aug 5, 2020Updated 5 years ago
- HDMI + GPU-pipeline + FFT☆14Mar 4, 2016Updated 10 years ago
- APB VIP (UVM)☆18Sep 6, 2018Updated 7 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-…☆30Dec 14, 2020Updated 5 years ago
- 奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）☆130Nov 13, 2019Updated 6 years ago
- OscillatorIMP ecosystem FPGA IP sources☆27Feb 22, 2026Updated last week