liuqdev / 8-bits-RISC-CPU-Verilog
Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC(精简指令集)CPU(中央处理器)简单结构和Verilog实现。
☆144Updated 6 years ago
Alternatives and similar repositories for 8-bits-RISC-CPU-Verilog:
Users that are interested in 8-bits-RISC-CPU-Verilog are comparing it to the libraries listed below
- CPU Design Based on RISCV ISA☆95Updated 9 months ago
- AXI协议规范中文翻译版☆141Updated 2 years ago
- ☆141Updated 3 weeks ago
- upgrade to e203 (a risc-v core)☆40Updated 4 years ago
- a simple riscv cpu☆22Updated 2 years ago
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆72Updated 5 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆196Updated last year
- a training-target implementation of rv32im, designed to be simple and easy to understand☆55Updated 3 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆126Updated 5 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆82Updated 3 years ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆111Updated 12 years ago
- 数字IC设计 学习笔记☆129Updated 3 years ago
- ☆63Updated 2 years ago
- ☆79Updated last month
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆26Updated 2 years ago
- 数字IC秋招项目、手撕代码☆34Updated 10 months ago
- A simple RISC-V CPU written in Verilog.☆62Updated 7 months ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- 《UVM实战》书本源代码和UVM 1.1d源码及Doc☆35Updated 4 years ago
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。☆221Updated 6 years ago
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆67Updated this week
- UVM实战随书源码☆49Updated 6 years ago
- ☆61Updated last year
- ☆59Updated 9 years ago
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆60Updated 2 years ago
- 3×3脉动阵列乘法器☆43Updated 5 years ago
- Cortex M0 based SoC☆71Updated 3 years ago
- 车牌识别,FPGA,2019全国大学生集成电路创新创业大赛☆135Updated 5 years ago
- ☆141Updated 4 years ago
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆23Updated last year