Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
☆162Jan 20, 2019Updated 7 years ago
Alternatives and similar repositories for 8-bits-RISC-CPU-Verilog
Users that are interested in 8-bits-RISC-CPU-Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 包括同步FIFO（输入输出位宽相同），异步FIFO（输入输出位宽相同），异步FIFO（能实现输出数据位宽是输入数据位宽的1/2或2倍）☆25Nov 7, 2022Updated 3 years ago
- Asynchronous fifo in verilog☆38Mar 20, 2016Updated 10 years ago
- Verilog implementation of a simple riscv cpu☆19Oct 28, 2021Updated 4 years ago
- Digital Component Design course project.☆20Nov 7, 2018Updated 7 years ago
- ☆18Jun 19, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- LeNet5 on PYNQ via HLS☆40May 29, 2023Updated 2 years ago
- 单周期 8指令 MIPS32CPU☆97Jan 2, 2026Updated 4 months ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Jul 17, 2014Updated 11 years ago
- verification of simple axi-based cache☆19May 14, 2019Updated 6 years ago
- 一步一步写MIPS CPU☆859Aug 4, 2021Updated 4 years ago
- Verilog Code for I2C Protocol☆19Nov 12, 2020Updated 5 years ago
- Verilog实现的简单五级流水线CPU，开发平台：Nexys3☆40Jul 9, 2015Updated 10 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- HDMI + GPU-pipeline + FFT☆14Mar 4, 2016Updated 10 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,541Apr 27, 2026Updated last week
- APB VIP (UVM)☆18Sep 6, 2018Updated 7 years ago
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆24Jul 20, 2023Updated 2 years ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆12Aug 6, 2025Updated 8 months ago
- Wishbone SATA Controller☆25Oct 16, 2025Updated 6 months ago
- ZYNQ-7000 based data transfer through TCP/IP protocol☆12Apr 20, 2023Updated 3 years ago
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆364Jan 12, 2018Updated 8 years ago
- Undergraduate digital circuit laboratory☆29Jan 4, 2024Updated 2 years ago
- Bitstream to Verilog decompiler for Lattice FPGA ECP5 chip.☆23Oct 10, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Verilog Model for W25Q128JVxIM Serial Flash Memory☆18Jun 7, 2020Updated 5 years ago
- Wraps the NVDLA project for Chipyard integration☆23Sep 2, 2025Updated 8 months ago
- ☆37Jul 28, 2025Updated 9 months ago
- A Verilog HDL model of the MOS 6502 CPU☆376Apr 8, 2023Updated 3 years ago
- HDLBits website practices & solutions☆789Dec 27, 2023Updated 2 years ago
- This repo is "NTHU VLSI System Design and Implementation" course project.☆13Mar 5, 2017Updated 9 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- This is a SPI Master Module Written in Verilog☆14Aug 9, 2018Updated 7 years ago
- Project Trellis database☆14Sep 15, 2025Updated 7 months ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- RISC-V CPU Core (RV32IM)☆1,712Sep 18, 2021Updated 4 years ago
- ARM中通过APB总线连接的UART模块☆71Feb 21, 2020Updated 6 years ago
- Verilog-A Preisach ferroelectric cap (PFECAP) simulation model for FET☆31Feb 16, 2020Updated 6 years ago
- a multiplier÷r verilog RTL file for RV32M instructions☆14Mar 17, 2020Updated 6 years ago
- A very primitive but hopefully self-educational CPU in Verilog☆153Jan 21, 2015Updated 11 years ago
- ☆18Jun 3, 2019Updated 6 years ago
- Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.☆13Apr 18, 2026Updated 2 weeks ago