Alternatives and similar repositories for verilog-doc:

Users that are interested in verilog-doc are comparing it to the libraries listed below

• CherrySprings / CherrySprings
  ☆18Updated last year
• DawnCarol / OpenC910_Modified
  commit rtl and build cosim env
  ☆15Updated last year
• sunyata000 / AMY_MCU
  A MCU implementation based PODES-M0O
  ☆18Updated 5 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆50Updated 2 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆38Updated last year
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆63Updated 2 years ago
• OSCPU / ysyxSoC
  ☆85Updated 2 months ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆53Updated 8 months ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆48Updated last year
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆61Updated last year
• kaitoukito / YSYX-NJU-Group
  YSYX RISC-V Project NJU Study Group
  ☆16Updated 3 months ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆50Updated 2 years ago
• sjj-star / automatically-generate-Wallace-Tree-VerilogHDL-code
  本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。
  ☆25Updated last year
• EECS150 / fpga_labs_sp22
  ☆28Updated 3 years ago
• risclite / verilog-divider
  a super-simple pipelined verilog divider. flexible to define stages
  ☆55Updated 5 years ago
• zhaishaomin / ring_network-based-multicore-
  多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency
  ☆23Updated 8 years ago
• pulp-platform / axi_llc
  ☆26Updated 2 weeks ago
• 2cc2ic / DMA-S2MM-and-MM2S
  Build an open source, extremely simple DMA.
  ☆21Updated 6 years ago
• woshiyyya / RISCV-CPU
  Write a CPU from scratch! (5-stage pipeline & 2-way-cache)
  ☆14Updated 5 years ago
• kunalg123 / icc2_workshop_collaterals
  This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…
  ☆31Updated 4 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• sequencer / arithmetic
  ☆33Updated last month
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆58Updated 3 years ago
• ljgibbslf / basic_cache_core
  ☆27Updated 4 years ago
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆30Updated 2 months ago
• lingscale / cc01
  ☆31Updated last month
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆51Updated 3 years ago
• OSCPU / yosys-sta
  ☆63Updated this week
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago