Alternatives and similar repositories for step_into_mips

Users that are interested in step_into_mips are comparing it to the libraries listed below

• loongson-education / nscscc-wiki
  NSCSCC 信息整合
  ☆251Updated 4 years ago
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆128Updated 4 years ago
• qing-2 / CPU
  单周期 8指令 MIPS32CPU
  ☆91Updated 3 years ago
• xiazhuo / nscc2022_personal
  NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）
  ☆77Updated last year
• Z-Y00 / Examples-in-book-write-your-own-cpu
  《自己动手写CPU》一书附带的文件
  ☆86Updated 7 years ago
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆289Updated last week
• zach0zhang / Single_instruction_cycle_OpenMIPS
  通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器
  ☆207Updated 3 years ago
• ykykzq / SimpleCPU
  基于LoongArch32/MIPS32指令集的七级流水线CPU。2023年龙芯杯（NSCSCC）个人赛参赛作品。
  ☆32Updated 4 months ago
• shinezyy / micro-arch-training
  How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design
  ☆587Updated last year
• y0fy / CO-lab-material-CQU
  重庆大学计算机组成原理、硬件综合设计实验材料
  ☆38Updated 4 years ago
• luyufan498 / CPU_start_from_0
  从零开始设计一个CPU (Verilog)
  ☆58Updated 4 years ago
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆85Updated 5 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆143Updated last year
• Azalea8 / riscv_cpu
  riscv指令集，单周期以及五级流水线CPU
  ☆81Updated 8 months ago
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆61Updated last year
• OSCPU / ysyx-workbench
  ☆156Updated last week
• fluctlight001 / cpu_for_nscscc2022_single
  2022年龙芯杯个人赛 单发射110M（含icache）
  ☆48Updated 3 years ago
• TheRainstorm / PiplineMIPS
  A 5-level pipelined MIPS CPU with branch prediction and great cache.
  ☆20Updated 4 years ago
• Googol2002 / NJU-ICS2021-PA
  2021年秋季学期 南京大学ICS课程 PA实验部分
  ☆129Updated 3 years ago
• rave1sking / single_cycle_RISCV_CPU_Design-32bit
  Verilog实现单周期非流水线32位RISCV指令集（45条）CPU
  ☆42Updated 4 years ago
• LSTM-Kirigaya / ComputerDesignExperiment
  计算机组成原理的实验，包括单周期CPU和五级流水线CPU的verilog实现
  ☆38Updated 4 years ago
• MaZirui2001 / USTC-NSCSCC
  中国科学技术大学龙芯杯参赛作品仓库合集
  ☆16Updated 11 months ago
• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆151Updated 6 years ago
• SinnLiu / CPU_Design_MIPS
  《CPU设计实战》学习记录及代码
  ☆13Updated last year
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆132Updated last year
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆179Updated 11 months ago
• 14010007517 / 2020NSCSCC
  Chongqing University 2020 NSCSCC
  ☆28Updated 4 years ago
• trivialmips / nontrivial-mips
  NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
  ☆602Updated 5 years ago
• NJU-ProjectN / nemu
  NJU EMUlator, a full system x86/mips32/riscv32/riscv64 emulator for teaching
  ☆1,038Updated 3 weeks ago
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆174Updated 4 years ago