viduraakalanka / HDL-Bits-SolutionsLinks
This is a repository containing solutions to the problem statements given in HDL Bits website.
☆358Updated 2 years ago
Alternatives and similar repositories for HDL-Bits-Solutions
Users that are interested in HDL-Bits-Solutions are comparing it to the libraries listed below
Sorting:
- ☆148Updated 3 weeks ago
- HDLBits website practices & solutions☆744Updated last year
- AMBA bus lecture material☆454Updated 5 years ago
- 在vscode上的数字设计开发插件☆384Updated 2 years ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆4Updated 8 months ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆359Updated last year
- Awesome ASIC design verification☆316Updated 3 years ago
- Must-have verilog systemverilog modules☆1,816Updated last week
- Contains the code examples from The UVM Primer Book sorted by chapters.☆560Updated 3 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,343Updated this week
- automatic-verilog based on vimscript☆267Updated last year
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆202Updated last year
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。☆254Updated 6 years ago
- ☆277Updated last year
- AXI协议规范中文翻译版☆159Updated 3 years ago
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆661Updated last year
- AMBA AXI VIP☆414Updated last year
- 数字IC设计 学习笔记☆151Updated 3 years ago
- Verilog I2C interface for FPGA implementation☆637Updated 5 months ago
- ☆222Updated 4 years ago
- Various HDL (Verilog) IP Cores☆823Updated 4 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆590Updated 7 years ago
- Verilog UART☆499Updated 5 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆498Updated 3 years ago
- ☆143Updated 4 years ago
- An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。☆410Updated last year
- Verilog AXI components for FPGA implementation☆1,788Updated 5 months ago
- this repository is vim cfg for verilog.☆50Updated last year
- Vivado诸多IP,包括图像处理等☆222Updated last year
- Verilog AXI stream components for FPGA implementation☆817Updated 5 months ago