This is a repository containing solutions to the problem statements given in HDL Bits website.
☆372Jul 16, 2023Updated 2 years ago
Alternatives and similar repositories for HDL-Bits-Solutions
Users that are interested in HDL-Bits-Solutions are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Must-have verilog systemverilog modules☆1,942Mar 12, 2026Updated 2 weeks ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, op…☆113Sep 17, 2022Updated 3 years ago
- HDLBits website practices & solutions☆784Dec 27, 2023Updated 2 years ago
- 帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目☆5,343May 15, 2022Updated 3 years ago
- My solution to the problem set on HDLBits.☆26Aug 6, 2020Updated 5 years ago
- NordVPN Threat Protection Pro™ • AdTake your cybersecurity to the next level. Block phishing, malware, trackers, and ads. Lightweight app that works with all browsers.
- IC design and development should be faster，simpler and more reliable☆1,985Dec 31, 2021Updated 4 years ago
- Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).☆93Sep 20, 2023Updated 2 years ago
- ☆145Oct 3, 2020Updated 5 years ago
- Verilog Model for W25Q128JVxIM Serial Flash Memory☆18Jun 7, 2020Updated 5 years ago
- The Ultra-Low Power RISC-V Core☆1,787Aug 6, 2025Updated 7 months ago
- All About HDL☆39Aug 21, 2019Updated 6 years ago
- Open-source high-performance RISC-V processor☆6,915Mar 23, 2026Updated last week
- Verilog Ethernet components for FPGA implementation☆2,902Feb 27, 2025Updated last year
- UVM Clock and Reset Agent☆14Jun 29, 2017Updated 8 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A small, light weight, RISC CPU soft core☆1,526Dec 8, 2025Updated 3 months ago
- Verilog AXI components for FPGA implementation☆1,996Feb 27, 2025Updated last year
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆25Jun 5, 2018Updated 7 years ago
- Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-…☆30Dec 14, 2020Updated 5 years ago
- Engineering Program on RTL Design for FPGA Accelerator☆33Aug 1, 2020Updated 5 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- Run rocket-chip on FPGA☆77Nov 16, 2025Updated 4 months ago
- Digital Interpolation Techniques Applied to Digital Signal Processing☆68Jun 24, 2024Updated last year
- HDL libraries and projects☆1,883Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- RTL, Cmodel, and testbench for NVDLA☆2,037Mar 2, 2022Updated 4 years ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆613Dec 24, 2021Updated 4 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- 为了学习UVM验证相关知识，需要动手尝试实际的项目。作为一个初学者，难以接触到实际的项目，于是我从夏宇闻老师的《Verilog数字系统设计教程》一书中，挑选出一个简单的小设计，作为我的验证对象，并围绕它编写了UVM验证环境。☆24Oct 9, 2020Updated 5 years ago
- Custom YOLOv4 for apple recognition (clean/damaged) on Alveo U280 accelerator card using Vitis AI framework.☆15Nov 1, 2021Updated 4 years ago
- -Designed and Verified a Bus Functional Model of AHB-LITE Protocol from scratch. -Developed Assertion based verification IP to verify the…☆24Dec 9, 2015Updated 10 years ago
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,827Mar 24, 2021Updated 5 years ago
- ☆14Oct 24, 2022Updated 3 years ago
- AXI协议规范中文翻译版☆171Jul 5, 2022Updated 3 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Hello Verilog by Mac + VSCode☆32Dec 26, 2025Updated 3 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,528Mar 18, 2026Updated last week
- 数字IC相关资料☆1,405Jul 1, 2025Updated 8 months ago
- An open-source Ternary Content Addressable Memory (TCAM) compiler.☆33Jul 19, 2024Updated last year
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…☆16Aug 26, 2021Updated 4 years ago
- A very simple and easy to understand RISC-V core.☆1,441Nov 9, 2023Updated 2 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆19Sep 14, 2023Updated 2 years ago