viduraakalanka / HDL-Bits-SolutionsLinks
This is a repository containing solutions to the problem statements given in HDL Bits website.
☆366Updated 2 years ago
Alternatives and similar repositories for HDL-Bits-Solutions
Users that are interested in HDL-Bits-Solutions are comparing it to the libraries listed below
Sorting:
- AMBA bus lecture material☆479Updated 5 years ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆21Updated 3 months ago
- HDLBits website practices & solutions☆762Updated last year
- ☆150Updated 3 weeks ago
- Awesome ASIC design verification☆331Updated 3 years ago
- 在vscode上的数字设计开发插件☆388Updated 2 years ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆580Updated 3 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆390Updated 2 months ago
- AXI协议规范中文翻译版☆165Updated 3 years ago
- automatic-verilog based on vimscript☆275Updated 2 years ago
- AMBA AXI VIP☆428Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆528Updated 4 years ago
- 数字IC设计 学习笔记☆156Updated 3 years ago
- ☆78Updated 2 months ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆224Updated 2 years ago
- Collect some IC textbooks for learning.☆170Updated 3 years ago
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆118Updated last month
- Reference examples and short projects using UVM Methodology☆283Updated 3 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆209Updated 2 years ago
- Verilog UART☆514Updated 8 months ago
- Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).☆93Updated 2 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆103Updated 3 years ago
- Verilog I2C interface for FPGA implementation☆657Updated 8 months ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆185Updated 7 years ago
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆318Updated 7 years ago
- An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。☆419Updated 2 years ago
- Must-have verilog systemverilog modules☆1,872Updated 3 months ago
- ☆144Updated 5 years ago
- CPU Design Based on RISCV ISA☆123Updated last year
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆597Updated 7 years ago