OpenIC-SIG / HDLBits-Chinese-gitbook
☆11Updated 4 years ago
Alternatives and similar repositories for HDLBits-Chinese-gitbook:
Users that are interested in HDLBits-Chinese-gitbook are comparing it to the libraries listed below
- eyeriss-chisel3☆40Updated 2 years ago
- ☆26Updated 4 years ago
- Ratatoskr NoC Simulator☆24Updated 3 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆61Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆53Updated 3 weeks ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- ☆14Updated 3 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated this week
- ☆25Updated last year
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- ☆26Updated 5 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆16Updated last week
- ☆31Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- sram/rram/mram.. compiler☆32Updated last year
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆38Updated 2 years ago
- ☆47Updated 2 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆20Updated 9 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆36Updated 6 months ago
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆12Updated last week
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆51Updated 5 years ago
- SystemC training aimed at TLM.☆27Updated 4 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆16Updated last year
- Project repo for the POSH on-chip network generator☆45Updated 3 weeks ago
- ☆35Updated 3 years ago
- ☆42Updated 6 years ago