zhangzek / Clock-Domain-Crossing-Design
Clock Domain Crossing Design(use MCP formulation without feedback)基于MCP不带反馈的跨时钟域设计
☆11Updated 5 years ago
Alternatives and similar repositories for Clock-Domain-Crossing-Design:
Users that are interested in Clock-Domain-Crossing-Design are comparing it to the libraries listed below
- Verilog and matlab implementation of tanh using Cordic algorithm☆9Updated 4 years ago
- ☆18Updated 2 years ago
- ☆31Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- ☆36Updated 9 years ago
- AXI Interconnect☆47Updated 3 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆31Updated 2 years ago
- AHB Bus lite v3.0☆15Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆36Updated 2 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆25Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆94Updated 4 years ago
- Build an open source, extremely simple DMA.☆21Updated 6 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 5 years ago
- upgrade to e203 (a risc-v core)☆40Updated 4 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆19Updated 12 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- ☆19Updated 2 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆60Updated 7 months ago
- SoC Based on ARM Cortex-M3☆29Updated 2 weeks ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 7 years ago
- 3×3脉动阵列乘法器☆43Updated 5 years ago
- ☆25Updated 3 years ago
- ☆12Updated 7 years ago
- ☆43Updated 2 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆19Updated 8 months ago
- 一个基于AXI接口的PL端卷积加速器,可由PS端调用☆11Updated last year
- ☆9Updated 4 years ago
- DMA controller for CNN accelerator☆13Updated 7 years ago