Clock Domain Crossing Design（use MCP formulation without feedback）基于MCP不带反馈的跨时钟域设计
☆12Jan 3, 2020Updated 6 years ago
Alternatives and similar repositories for Clock-Domain-Crossing-Design
Users that are interested in Clock-Domain-Crossing-Design are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆10Aug 12, 2021Updated 4 years ago
- ☆20Aug 22, 2022Updated 3 years ago
- Vivado project for the SP701 Imaging application project☆13Apr 1, 2020Updated 6 years ago
- ☆76Aug 30, 2022Updated 3 years ago
- Projects for the Scarab Minispartan6+ FPGA board☆14Jun 20, 2015Updated 10 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 3×3脉动阵列乘法器☆50Sep 18, 2019Updated 6 years ago
- Network on Chip for MPSoC☆28May 20, 2026Updated 3 weeks ago
- ☆21Dec 31, 2021Updated 4 years ago
- WinUSB implementation for the ZYNQ platform (Zybo board)☆28Aug 27, 2018Updated 7 years ago
- 用于 MobileNetV3 在自定义数据集上的量化，模型压缩90%而精度几乎不受影响，论文：HAQ: Hardware-Aware Automated Quantization with Mixed Precision☆20Jul 10, 2021Updated 4 years ago
- 在FPGA上实现SRIO收发控制器☆11Sep 30, 2022Updated 3 years ago
- 基于Point Transformers复现点云分割任务，并使用HAQ算法进行自动量化压缩，几乎不影响精度☆26Aug 25, 2022Updated 3 years ago
- Paper list for accleration of transformers☆14Jul 1, 2023Updated 2 years ago
- eyeriss-chisel3☆41May 2, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Quantization in the Jagged Loss Landscape of Vision Transformers☆13Oct 22, 2023Updated 2 years ago
- ☆42Apr 28, 2019Updated 7 years ago
- Course resource for the optimization algorithm course in spring 2021. The course is lectured by prof. Zhouwang Yang.☆16Jan 26, 2022Updated 4 years ago
- 学习AXI接口，以及xilinx DDR3 IP使用☆40Mar 6, 2017Updated 9 years ago
- ☆34Nov 26, 2019Updated 6 years ago
- Switch-based Training Acceleration for Machine Learning (SwitchML)☆16Apr 13, 2021Updated 5 years ago
- 基于KHドット人形町16衍生的中文像素字体 / A Chinese pixel font derived from KH Dot Ningyouchou 16.☆62May 11, 2026Updated last month
- MTCNN face detection using OpenCV☆17Jan 5, 2021Updated 5 years ago
- gem5 相关中文笔记☆16Dec 2, 2021Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Verilog based FPGA Design of SHA256 Simulated on ModelSim☆24May 18, 2018Updated 8 years ago
- The polymerization of all frequently-used UESTC online services. | 电子科技大学 线上服务集合索引☆21Oct 1, 2022Updated 3 years ago
- Research enablement kit for designing and prototyping a Cortex-M0–based SoC with custom IP integration (education, research)☆17Jun 13, 2025Updated last year
- AXI Interconnect☆57Aug 20, 2021Updated 4 years ago
- Revolutionize your development workflow with AI-powered code assistance, automating mock tests, suggestions, and unit test generation in …☆33Feb 27, 2025Updated last year
- Pytorch implementation of our paper accepted by ECCV 2022-- Fine-grained Data Distribution Alignment for Post-Training Quantization☆16Sep 13, 2022Updated 3 years ago
- Train neural networks with joint quantization and pruning on both weights and activations using any pytorch modules☆42Sep 19, 2022Updated 3 years ago
- ☆12May 31, 2016Updated 10 years ago
- ☆17Nov 25, 2017Updated 8 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆65Updated this week
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- IP operations in verilog (simulation and implementation on ice40)☆64Oct 24, 2019Updated 6 years ago
- Quite OK Image FPGA Encoder and Decoder☆24May 20, 2023Updated 3 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆49Oct 14, 2022Updated 3 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- 基于乐鑫 ESP32/ESP32-S2/S3 开发的小型无人机解决方案、基于北京理工大学自动化学院OLDX多旋翼开发平台（OLDX-FC）、基于正点原子ATK-F405☆21Apr 22, 2023Updated 3 years ago