zhangzek / Clock-Domain-Crossing-DesignLinks
Clock Domain Crossing Design(use MCP formulation without feedback)基于MCP不带反馈的跨时钟域设计
☆11Updated 5 years ago
Alternatives and similar repositories for Clock-Domain-Crossing-Design
Users that are interested in Clock-Domain-Crossing-Design are comparing it to the libraries listed below
Sorting:
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago
- ☆20Updated 2 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- ☆13Updated 8 years ago
- ☆12Updated 9 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Updated 12 years ago
- ☆10Updated 5 years ago
- ☆34Updated 6 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated 7 months ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆23Updated 5 years ago
- ☆36Updated 9 years ago
- ☆59Updated 2 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆66Updated 11 months ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆12Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- AHB Bus lite v3.0☆16Updated 6 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- ☆15Updated 2 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- EE577b-Course-Project☆17Updated 5 years ago
- soc integration script and integration smoke script☆23Updated 2 years ago
- ☆26Updated 4 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 4 years ago
- Basic floating-point components for RISC-V processors☆10Updated 7 years ago
- DMA controller for CNN accelerator☆13Updated 8 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago