Starrynightzyq / ZYNQ-PYNQ-Z2-GobangView external linksLinks
2018第二届全国大学生FPGA创新设计邀请赛的作品
☆63Dec 21, 2018Updated 7 years ago
Alternatives and similar repositories for ZYNQ-PYNQ-Z2-Gobang
Users that are interested in ZYNQ-PYNQ-Z2-Gobang are comparing it to the libraries listed below
Sorting:
- 车牌识别,FPGA,2019全国大学生集成电路创新创业大赛☆148Dec 8, 2019Updated 6 years ago
- Imaging application using MIPI and DisplayPort to process image☆25Feb 13, 2020Updated 6 years ago
- njtech digital design. a fpga digital alarm system with Nexys A7 100T☆54Jun 11, 2019Updated 6 years ago
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆14Jun 1, 2017Updated 8 years ago
- 开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车，分为两个部分，控制器部分和小车部分，通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势，从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…☆13Mar 10, 2019Updated 6 years ago
- ☆35Mar 10, 2021Updated 4 years ago
- 关于数字IC的笔试面试题☆14Nov 17, 2019Updated 6 years ago
- This is just for Takk_Zynq_Labs test.☆27Jan 14, 2022Updated 4 years ago
- Digital Standard Cells based SAR ADC☆14Aug 5, 2021Updated 4 years ago
- FPGA-CNN Application for fruit detection based on Logos-PGL22G Board☆14Aug 24, 2022Updated 3 years ago
- ASIC Design of the openSPARC Floating Point Unit☆15Mar 13, 2017Updated 8 years ago
- FPGA Technology Exchange Group相关文件管理☆67Jan 3, 2026Updated last month
- 基于arm cortex-m0内核的xillinx fpga sopc工程项目☆13May 28, 2019Updated 6 years ago
- ☆16Dec 16, 2021Updated 4 years ago
- 这是我所开发的两个项目，包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统☆96Sep 25, 2017Updated 8 years ago
- ⚙️ 基于 Zynq-7 全可编程 SoC 的设计☆38Dec 31, 2021Updated 4 years ago
- Open source zynq platform☆18May 25, 2018Updated 7 years ago
- ☆15May 9, 2020Updated 5 years ago
- ☆16Mar 18, 2024Updated last year
- Deprecated ADI fork ➡️ analogdevicesinc/u-boot☆18Nov 26, 2025Updated 2 months ago
- 开源SDN交换机项目-FAST 项目背景 现有SDN交换机开源项目（如OVS）主要基于软件编写，虽然其分组转发查表等功能在内核 中实现，但分组转发性能仍然是主要问题。将软件SDN交换机的分组转发模块卸载到FPGA中实现，不仅能提高交换性能，而且利用FPGA可重…☆41Apr 23, 2017Updated 8 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Jun 10, 2018Updated 7 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Feb 21, 2020Updated 5 years ago
- 基于verilog实现了ISP图像处理IP☆316Nov 28, 2022Updated 3 years ago
- verilog☆21Jun 26, 2023Updated 2 years ago
- minimal code to access ps DDR from PL☆22Oct 18, 2019Updated 6 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆21Apr 9, 2020Updated 5 years ago
- UART To SPI☆19Jul 17, 2014Updated 11 years ago
- AXI MIPI CSI2 RX FPGA core and kernel driver☆19Jul 4, 2015Updated 10 years ago
- Python Utilities to use Xilinx Vivado Tools from Python Scripts☆22Oct 18, 2020Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Jan 4, 2018Updated 8 years ago
- Connecting FPGA and MCU using Ethernet RMII☆23Jan 23, 2016Updated 10 years ago
- 集成电路设计大赛ARM杯作品，获得2021年ARM企业杯☆16Sep 26, 2021Updated 4 years ago
- An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。☆334Sep 15, 2023Updated 2 years ago
- an opensource project to enable TSN research☆41Apr 26, 2022Updated 3 years ago
- To help machines learn what we human beings are doing via a camera is important. Once it comes true, machines can make different response…☆54Jun 28, 2018Updated 7 years ago
- ☆23Dec 7, 2019Updated 6 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆69Feb 13, 2025Updated last year
- 中文版 Parallel Programming for FPGAs☆761Aug 21, 2024Updated last year