Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…
☆20Aug 6, 2025Updated last year
Alternatives and similar repositories for 32-Verilog-Mini-Projects
Users that are interested in 32-Verilog-Mini-Projects are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆210Jan 29, 2024Updated 2 years ago
- Implementing Different Adder Structures in Verilog☆77Sep 3, 2019Updated 6 years ago
- This repository contains source code for past labs and projects involving FPGA and Verilog based designs☆122Oct 2, 2019Updated 6 years ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆155Jul 17, 2022Updated 4 years ago
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆62Nov 30, 2022Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- DDR2 memory controller written in Verilog☆84Feb 28, 2012Updated 14 years ago
- Image Processing Toolbox in Verilog using Basys3 FPGA☆241May 20, 2025Updated last year
- Must-have verilog systemverilog modules☆2,006Mar 12, 2026Updated 4 months ago
- 5-stage pipelined 32-bit MIPS microprocessor in Verilog☆146Apr 3, 2020Updated 6 years ago
- the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.☆50Jul 18, 2020Updated 6 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆82Oct 7, 2022Updated 3 years ago
- AMBA bus lecture material☆547Jan 21, 2020Updated 6 years ago
- synthesiseable ieee 754 floating point library in verilog☆750Mar 13, 2023Updated 3 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆20Jan 27, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆41May 10, 2019Updated 7 years ago
- ☆56Jun 19, 2021Updated 5 years ago
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆544Jul 18, 2025Updated last year
- Implementation of CNN using Verilog☆248Oct 13, 2017Updated 8 years ago
- Verilog UART☆575Feb 27, 2025Updated last year
- HDLBits website practices & solutions☆806Dec 27, 2023Updated 2 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆626Mar 15, 2018Updated 8 years ago
- Solution to COA LAB Assgn, IIT Kharagpur☆38Jan 10, 2019Updated 7 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆143Jul 31, 2022Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Various HDL (Verilog) IP Cores☆929Jul 1, 2021Updated 5 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆470Feb 13, 2026Updated 5 months ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆148May 14, 2021Updated 5 years ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 4 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆115Jul 2, 2023Updated 3 years ago
- Verilog library for ASIC and FPGA designers☆1,435May 8, 2024Updated 2 years ago
- This repository contains all labs done as a part of the Embedded Logic and Design course.☆28Jun 10, 2018Updated 8 years ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆124Jan 26, 2013Updated 13 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆124Jul 9, 2023Updated 3 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.☆67Nov 25, 2020Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆124Apr 3, 2026Updated 4 months ago
- Verilog AXI components for FPGA implementation☆2,109Feb 27, 2025Updated last year
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆21Aug 5, 2023Updated 3 years ago
- 30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills a…☆73Sep 30, 2023Updated 2 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆622Oct 10, 2021Updated 4 years ago
- 100 Days of RTL☆423Aug 15, 2024Updated last year