Alternatives and similar repositories for Marian

Users that are interested in Marian are comparing it to the libraries listed below

• asveske / apb_vip
  APB VIP (UVM)
  ☆18Updated 7 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆76Updated last month
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆134Updated 3 weeks ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆94Updated last month
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆43Updated last year
• chipsalliance / uvm-verilator
  ☆111Updated last month
• pulp-platform / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆20Updated last month
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 3 years ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆124Updated this week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆79Updated last year
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆85Updated 2 months ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 6 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆191Updated 2 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆87Updated 4 years ago
• pulp-platform / axi_llc
  ☆33Updated last month
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆61Updated 3 weeks ago
• vlsi-lab / len5
  LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
  ☆19Updated 2 months ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆99Updated 4 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 5 months ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆72Updated last year
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆62Updated last year
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆33Updated 3 weeks ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆34Updated 7 months ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆86Updated 4 years ago
• muneebullashariff / uart_vip
  Verification IP for UART protocol
  ☆21Updated 5 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 10 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆43Updated 4 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆81Updated 9 months ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆76Updated 5 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆73Updated this week