Alternatives and similar repositories for Marian:

Users that are interested in Marian are comparing it to the libraries listed below

• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆62Updated 2 weeks ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆86Updated last month
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆83Updated 4 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆51Updated 5 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆63Updated 9 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆131Updated 3 weeks ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆63Updated 3 months ago
• pulp-platform / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆19Updated last month
• riscv-ovpsim / imperas-riscv-tests
  ☆170Updated last year
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆49Updated 2 weeks ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆69Updated last week
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆38Updated 10 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 10 months ago
• vlsi-lab / len5
  LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
  ☆16Updated 10 months ago
• vherdt / riscv-vp
  RISC-V Virtual Prototype
  ☆41Updated 3 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆185Updated this week
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆65Updated 8 months ago
• chipsalliance / uvm-verilator
  ☆89Updated last year
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆43Updated 4 months ago
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆37Updated 3 weeks ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 4 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆186Updated 8 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆88Updated 2 weeks ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆101Updated this week
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆30Updated 10 months ago
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆50Updated 3 years ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆86Updated last week
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆50Updated 3 months ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆56Updated last year