pulp-platform / quadrilatero
matrix-coprocessor for RISC-V
☆10Updated last month
Related projects ⓘ
Alternatives and complementary repositories for quadrilatero
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆12Updated 9 months ago
- CORE-V MCU UVM Environment and Test Bench☆17Updated 3 months ago
- ☆10Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆18Updated last month
- ☆37Updated 5 years ago
- ☆73Updated last year
- ☆29Updated 2 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 7 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆58Updated last week
- ☆22Updated 5 years ago
- Design and UVM-TB of RISC -V Microprocessor☆13Updated 4 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆22Updated last month
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated 2 weeks ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆23Updated last week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆57Updated 3 weeks ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 5 months ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆31Updated last year
- Original test vector of RISC-V Vector Extension☆11Updated 3 years ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆20Updated 4 months ago
- DUTH RISC-V Superscalar Microprocessor☆28Updated 2 weeks ago
- SoC Based on ARM Cortex-M3☆25Updated 5 months ago
- The official NaplesPU hardware code repository☆11Updated 5 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆26Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- DUTH RISC-V Microprocessor☆19Updated this week
- Platform Level Interrupt Controller☆35Updated 6 months ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆25Updated last week