ucb-bar / onnxruntime-riscvLinks
Fork of upstream onnxruntime focused on supporting risc-v accelerators
☆88Updated 2 years ago
Alternatives and similar repositories for onnxruntime-riscv
Users that are interested in onnxruntime-riscv are comparing it to the libraries listed below
Sorting:
- A DSL for Systolic Arrays☆82Updated 6 years ago
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆88Updated last month
- ☆86Updated 2 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆155Updated 9 months ago
- PyTorch model to RTL flow for low latency inference☆129Updated last year
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆58Updated last month
- ☆37Updated 3 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆229Updated 2 years ago
- ☆61Updated last week
- Ventus GPGPU ISA Simulator Based on Spike☆49Updated last month
- ☆116Updated last week
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆110Updated 2 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆60Updated 3 years ago
- A tool to deploy Deep Neural Networks on PULP-based SoC's☆90Updated 3 months ago
- ☆87Updated this week
- ☆33Updated 2 years ago
- ☆46Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 8 months ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- Release of stream-specialization software/hardware stack.☆119Updated 2 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆156Updated last year
- Eyeriss chip simulator☆38Updated 5 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆202Updated 5 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆78Updated last month
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆143Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- A scalable High-Level Synthesis framework on MLIR☆282Updated last year
- ☆37Updated last year
- RiVEC Bencmark Suite☆123Updated 11 months ago
- ☆71Updated 5 years ago