Alternatives and similar repositories for onnxruntime-riscv:

Users that are interested in onnxruntime-riscv are comparing it to the libraries listed below

• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆214Updated 2 years ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆132Updated last month
• zeasa / nvdla-compiler
  ☆43Updated 5 years ago
• makslevental / openhls
  PyTorch model to RTL flow for low latency inference
  ☆126Updated last year
• tum-ei-eda / muriscv-nn
  muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.
  ☆74Updated 2 weeks ago
• GATECH-EIC / AutoDNNchip
  ☆70Updated 5 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆77Updated 7 months ago
• WuDan0399 / Integrate-NVDLA-and-TVM
  ☆29Updated 2 years ago
• Xilinx / mlir-air
  ☆91Updated last week
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆42Updated 3 weeks ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆89Updated 5 months ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆79Updated 6 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 3 years ago
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆186Updated 4 years ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆121Updated 2 weeks ago
• TeCSAR-UNCC / gem5-SALAM
  ☆91Updated last year
• Xilinx / pyxir
  ☆37Updated 2 years ago
• thousrm / universal_NPU-CNN_accelerator
  hardware design of universal NPU(CNN accelerator) for various convolution neural network
  ☆111Updated 2 weeks ago
• UIUC-ChenLab / scalehls
  A scalable High-Level Synthesis framework on MLIR
  ☆252Updated 10 months ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆50Updated 2 weeks ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆48Updated last week
• Accelergy-Project / timeloop-accelergy-exercises
  Exercises for exploring the Fibertree, Timeloop and Accelergy tools
  ☆90Updated 2 months ago
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆55Updated 3 years ago
• ucb-bar / gemmini-rocc-tests
  Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
  ☆55Updated last month
• PSAL-POSTECH / ONNXim
  ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference
  ☆99Updated last month
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆57Updated 3 years ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆150Updated last year
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆121Updated last year
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆131Updated this week
• XUANTIE-RV / csi-nn2
  An optimized neural network operator library for chips base on Xuantie CPU.
  ☆87Updated 8 months ago