Alternatives and similar repositories for srv32

Users that are interested in srv32 are comparing it to the libraries listed below

• mathis-s / SoomRV
  A simple superscalar out-of-order RISC-V microprocessor
  ☆212Updated 6 months ago
• eisl-nctu / aquila
  Aquila: a 32-bit RISC-V processor for Xilinx FPGAs.
  ☆32Updated last year
• yutongshen / RISC-V_SoC
  ☆38Updated 2 years ago
• s094392 / riscv-bare-metal
  A RISC-V bare metal example
  ☆49Updated 3 years ago
• yutongshen / RISC-V-Emulator
  ☆31Updated 6 months ago
• riscvarchive / riscv-code-size-reduction
  ☆149Updated last year
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆155Updated 3 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆101Updated 3 years ago
• accomdemy / accomdemy_rv32i
  伴伴學 RISC-V RV32I Architecture CPU
  ☆30Updated 2 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 9 months ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆59Updated 9 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆244Updated 9 months ago
• riscv / riscv-CMOs
  ☆89Updated 3 years ago
• raster-gpu / raster-i
  A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L),…
  ☆239Updated 7 months ago
• RinHizakura / riscv-emulator
  A project for learning RISC-V architecture purpose
  ☆25Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆119Updated last month
• michaeljclark / riscv-probe
  Simple machine mode program to probe RISC-V control and status registers
  ☆123Updated 2 years ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated 9 months ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆174Updated 8 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆266Updated 4 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆160Updated 5 years ago
• sysprog21 / semu
  A minimalist RISC-V system emulator capable of running Linux kernel
  ☆266Updated 2 weeks ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆274Updated this week
• riscv-software-src / riscof
  ☆86Updated 4 months ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆145Updated 3 weeks ago
• ninolomata / bao-cva6-guide
  ☆12Updated last year
• Mariotti94 / WebRISC-V
  WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
  ☆152Updated 2 months ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆142Updated 5 years ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆186Updated last month
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆218Updated 3 months ago