vlsiexcellence / Static-Timing-Analysis-Full-Course
Static Timing Analysis Full Course
☆52Updated 2 years ago
Alternatives and similar repositories for Static-Timing-Analysis-Full-Course:
Users that are interested in Static-Timing-Analysis-Full-Course are comparing it to the libraries listed below
- Introductory course into static timing analysis (STA).☆90Updated 5 months ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆58Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆57Updated last year
- ☆154Updated 2 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆68Updated 4 years ago
- ☆17Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆56Updated 2 years ago
- Python Tool for UVM Testbench Generation☆52Updated 11 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆23Updated last year
- ☆15Updated 2 years ago
- ☆43Updated 3 years ago
- SystemVerilog UVM testbench example☆30Updated 11 months ago
- ☆49Updated 8 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆56Updated 2 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆58Updated 4 years ago
- Asynchronous fifo in verilog☆33Updated 9 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆53Updated last year
- 5 Day TCL begginer to advanced training workshop by VSD☆17Updated last year
- Structured UVM Course☆40Updated last year
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆44Updated 3 years ago
- Architectural design of data router in verilog☆29Updated 5 years ago
- ☆40Updated 3 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆71Updated 2 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- SystemVerilog modules and classes commonly used for verification☆47Updated 3 months ago
- ☆10Updated 2 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago