TinyTapeout / tinytapeout-02
TinyTapeout-02 submission repository
☆28Updated last year
Alternatives and similar repositories for tinytapeout-02
Users that are interested in tinytapeout-02 are comparing it to the libraries listed below
Sorting:
- SAR ADC on tiny tapeout☆38Updated 3 months ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/☆47Updated last month
- Submission template for Tiny Tapeout 8 - Verilog HDL Projects☆18Updated 10 months ago
- ☆19Updated 4 years ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆17Updated last month
- Test Chip General Purpose OpAmp using Skywater SKY130 PDK☆18Updated 4 years ago
- A fully-integrated FT8 protocol receiver on 130nm CMOS☆60Updated 2 years ago
- Documenting the Lattice ECP5 bit-stream format.☆54Updated last year
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆72Updated 3 years ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆37Updated this week
- Flip flop setup, hold & metastability explorer tool☆34Updated 2 years ago
- A pipelined RISC-V processor☆55Updated last year
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆31Updated 4 years ago
- ☆39Updated 2 years ago
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…☆29Updated 2 months ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆21Updated 3 years ago
- Submission template for Tiny Tapeout 03☆20Updated last year
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 6 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆44Updated last year
- This repository contains small example designs that can be used with the open source icestorm flow.☆147Updated 3 years ago
- FPGA board-level debugging and reverse-engineering tool☆37Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆91Updated 8 months ago
- FPGA examples on Google Colab☆22Updated last year
- SoftCPU/SoC engine-V☆54Updated last month
- ☆23Updated last year
- Experiments with Yosys cxxrtl backend☆48Updated 4 months ago