A small RISC-V core (SystemVerilog)
☆33Aug 26, 2019Updated 6 years ago
Alternatives and similar repositories for nanoFOX
Users that are interested in nanoFOX are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆25May 20, 2020Updated 6 years ago
- Contains source code for sin/cos table verification using UVM☆22Mar 9, 2021Updated 5 years ago
- Open source firmware for iCELink on iCESugar nano FPGA dev board.☆15Jul 3, 2022Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- Example files for the book FPGA SIMULATION☆23Apr 6, 2017Updated 9 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- GDB interface utility for MIPS processors, including PIC32☆27Sep 20, 2019Updated 6 years ago
- ☆14Nov 11, 2015Updated 10 years ago
- RV32I by cats☆15Sep 4, 2023Updated 2 years ago
- Verilog (SystemVerilog) coding style☆42Jan 7, 2019Updated 7 years ago
- Repository gathering basic modules for CDC purpose☆61Dec 31, 2019Updated 6 years ago
- FPGA examples for 8bitworkshop.com☆30May 23, 2019Updated 7 years ago
- Single-Cycle RISC-V Processor in systemverylog☆25Apr 23, 2019Updated 7 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆22Apr 26, 2026Updated 3 weeks ago
- Mastering FPGASIC Book☆18Oct 26, 2025Updated 6 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Spiking Neural Network Accelerator☆15May 18, 2022Updated 4 years ago
- Lessons for learning 3D computer vision in BoofCV☆14Apr 21, 2019Updated 7 years ago
- Examples of unions, interfaces, and assertions in SystemVerilog☆13Aug 31, 2013Updated 12 years ago
- VHDL dependency analyzer☆25Mar 10, 2020Updated 6 years ago
- A Hardware MD5 Cracker for the Cyclone V SoC☆12Mar 25, 2015Updated 11 years ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆378Jul 12, 2017Updated 8 years ago
- ☆65Nov 9, 2021Updated 4 years ago
- Video digitizer add-on module for DE2-115 FPGA development board.☆13Apr 17, 2017Updated 9 years ago
- DUTH RISC-V Microprocessor☆26Apr 5, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆64Jan 8, 2019Updated 7 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Jun 12, 2023Updated 2 years ago
- An FPGA/STM32 based frequency counter with an Android user interface☆31Apr 9, 2016Updated 10 years ago
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆14Sep 22, 2025Updated 8 months ago
- 10 Gbit/s flexible and extensible Ethernet FPGA-based traffic generator☆11Oct 3, 2014Updated 11 years ago
- ☆19Feb 23, 2021Updated 5 years ago
- A dedicated graphical processor for ray tracing☆22Jun 7, 2021Updated 4 years ago
- A neural network built in Verilog for the DE1-SoC FPGA board for handwritten digit recognition.☆18Oct 11, 2019Updated 6 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Jun 14, 2018Updated 7 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Must-have verilog systemverilog modules☆38May 1, 2022Updated 4 years ago
- CPU microarchitecture, step by step☆208Nov 1, 2020Updated 5 years ago
- ☆11Jul 12, 2023Updated 2 years ago
- A library for standard containers and their associated algorithms.☆12Feb 28, 2025Updated last year
- Static Timing Analysis Full Course☆68Jan 14, 2023Updated 3 years ago
- Полезные ресурсы по тематике FPGA / ПЛИС☆180Oct 28, 2025Updated 6 months ago
- Implementation of a circular queue in hardware using verilog.☆17Mar 22, 2019Updated 7 years ago