nrot / WaveGenLinks
☆11Updated last year
Alternatives and similar repositories for WaveGen
Users that are interested in WaveGen are comparing it to the libraries listed below
Sorting:
- Mastering FPGASIC Book☆18Updated 3 years ago
- human-in-the-loop HDL training tool☆38Updated last year
- Contains source code for sin/cos table verification using UVM☆20Updated 4 years ago
- Репозиторий факультатива по функциональной верификации НИУ МИЭТ☆12Updated 9 months ago
- Методические материалы к лабораторным работам дисциплины "Проектирование цифровых устройств на языке Verilog"☆11Updated last year
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆17Updated 6 months ago
- System on Chip toolkit for Amaranth HDL☆90Updated 7 months ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"☆36Updated last week
- sample VCD files☆37Updated last year
- PicoRV☆44Updated 5 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 3 years ago
- Small footprint and configurable Inter-Chip communication cores☆58Updated last week
- Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)☆32Updated 11 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆93Updated 9 months ago
- Nix flake for openXC7☆38Updated 2 months ago
- ☆23Updated 5 years ago
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆25Updated last year
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆24Updated 6 months ago
- USB virtual model in C++ for Verilog☆30Updated 7 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆44Updated last week
- A configurable USB 2.0 device core☆31Updated 4 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆63Updated last week
- ☆47Updated 3 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.☆18Updated 3 years ago
- Методические материалы курса "Практикум по ПЛИС"☆29Updated last week
- Board and connector definition files for nMigen☆30Updated 4 years ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆97Updated 2 years ago