nrot / WaveGen
☆11Updated last year
Related projects ⓘ
Alternatives and complementary repositories for WaveGen
- Mastering FPGASIC Book☆18Updated 2 years ago
- Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek sec…☆29Updated this week
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆25Updated last year
- RISC-V Processor written in Amaranth HDL☆31Updated 2 years ago
- Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"☆32Updated last month
- sample VCD files☆36Updated 8 months ago
- ☆46Updated 3 years ago
- Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chil…☆44Updated last week
- System on Chip toolkit for Amaranth HDL☆84Updated 3 weeks ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 2 years ago
- Методические материалы к лабораторным работам дисциплины "Проектирование цифровых устройств на языке Verilog"☆11Updated last year
- Naive Educational RISC V processor☆71Updated 3 weeks ago
- User-friendly explanation of Yosys options☆111Updated 3 years ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆92Updated last year
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- Board and connector definition files for nMigen☆29Updated 4 years ago
- Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.☆17Updated 3 years ago
- ☆35Updated 2 years ago
- PicoRV☆43Updated 4 years ago
- Small footprint and configurable Inter-Chip communication cores☆54Updated last month
- A padring generator for ASICs☆22Updated last year
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆22Updated 2 weeks ago
- Wishbone interconnect utilities☆36Updated 5 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆42Updated this week
- Python script to transform a VCD file to wavedrom format☆73Updated 2 years ago
- USB virtual model in C++ for Verilog☆28Updated 3 weeks ago
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- Spen's Official OpenOCD Mirror☆47Updated 8 months ago
- human-in-the-loop HDL training tool☆33Updated 8 months ago
- Nix flake for openXC7☆26Updated 2 months ago