Alternatives and similar repositories for WaveGen

Users that are interested in WaveGen are comparing it to the libraries listed below

• iDoka / book-mastering-fpgasic
  Mastering FPGASIC Book
  ☆18Updated 3 months ago
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• MPSU / PCU-Verilog-labs
  Методические материалы к лабораторным работам дисциплины "Проектирование цифровых устройств на языке Verilog"
  ☆12Updated 2 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆98Updated last week
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 4 years ago
• NickolayTernovoy / risc-v_awesome_list
  ☆48Updated 4 years ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• vlotnik / uvm_sin_cos_table
  Contains source code for sin/cos table verification using UVM
  ☆21Updated 4 years ago
• wavedrom / vcd-samples
  sample VCD files
  ☆41Updated last month
• serge0699 / verif_elective_miet
  Репозиторий факультатива по функциональной верификации НИУ МИЭТ
  ☆16Updated last year
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆32Updated 3 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆110Updated this week
• FPGA-InsideOut / hdlgadgets
  human-in-the-loop HDL training tool
  ☆40Updated last year
• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆47Updated 3 months ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆47Updated this week
• iDoka / eda-scripts
  Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)
  ☆35Updated last year
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆39Updated 4 years ago
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆26Updated 7 months ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆88Updated 3 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• MPSU / MIRISCV
  Открытое RISC-V процессорное ядро MIRISCV для образовательных целей
  ☆23Updated last year
• EvgenyMuryshkin / QuokkaEvaluation
  Example projects for Quokka FPGA toolkit
  ☆37Updated 3 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆74Updated 4 years ago
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆187Updated last year
• openXC7 / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆56Updated 2 months ago
• regymm / GenZ
  The open-source Zynq 7000 BSP generator for openXC7
  ☆53Updated last year
• ekiwi / icesugar-chisel
  Chisel Examples for the iCESugar FPGA Board
  ☆12Updated 4 years ago
• toem / impulse.vscode
  impulse is an event and waveform visualization and analysis workbench (simulation, traces, logs) which helps engineers to comfortably und…
  ☆29Updated 2 months ago
• asicguy / spacex_uart
  Project and presentation for SpaceX Application
  ☆14Updated 8 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆50Updated 3 weeks ago