FPGA-InsideOut / hdlgadgetsLinks
human-in-the-loop HDL training tool
☆38Updated last year
Alternatives and similar repositories for hdlgadgets
Users that are interested in hdlgadgets are comparing it to the libraries listed below
Sorting:
- Репозиторий факультатива по функциональной верификации НИУ МИЭТ☆13Updated last year
- Contains source code for sin/cos table verification using UVM☆20Updated 4 years ago
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆19Updated 8 months ago
- Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"☆43Updated last month
- FPGA exercise for beginners☆125Updated 2 weeks ago
- SystemVerilog language-oriented exercises☆110Updated 2 months ago
- Drawio => VHDL and Verilog☆57Updated last year
- Полезные ресурсы по тематике FPGA / ПЛИС☆167Updated 9 months ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- Example of Python and PyTest powered workflow for a HDL simulation☆15Updated 4 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆24Updated last month
- Control and Status Register map generator for HDL projects☆125Updated 3 months ago
- An open-source HDL register code generator fast enough to run in real time.☆73Updated last week
- SystemVerilog Linter based on pyslang☆31Updated 3 months ago
- Python script to transform a VCD file to wavedrom format☆78Updated 3 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆107Updated 4 years ago
- Converts the SystemRDL data into pdf Register specification☆14Updated last year
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 4 years ago
- RISC-V Nox core☆68Updated last month
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆46Updated 4 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆131Updated last week
- Examples for using pyuvm☆19Updated last year
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆64Updated 2 weeks ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆75Updated last month
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆44Updated 7 months ago
- hardware library for hwt (= ipcore repo)☆43Updated last month
- Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем☆21Updated 4 months ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆34Updated 6 months ago
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆25Updated 5 months ago
- Generate address space documentation HTML from compiled SystemRDL input☆56Updated 2 months ago