Alternatives and similar repositories for awesome-functional-verification

Users that are interested in awesome-functional-verification are comparing it to the libraries listed below

• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆43Updated 2 months ago
• serge0699 / synth_school_verif_tasks
  Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем
  ☆22Updated 5 months ago
• vlsiexcellence / Static-Timing-Analysis-Full-Course
  Static Timing Analysis Full Course
  ☆60Updated 2 years ago
• MPSU / MIRISCV
  Открытое RISC-V процессорное ядро MIRISCV для образовательных целей
  ☆19Updated 9 months ago
• yuri-panchul / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆110Updated 2 months ago
• chipdesignschool / basics-graphics-music
  FPGA exercise for beginners
  ☆37Updated 2 weeks ago
• FPGA-Systems / fpga-awesome-list
  Полезные ресурсы по тематике FPGA / ПЛИС
  ☆167Updated 10 months ago
• chipdesignschool / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆49Updated 2 months ago
• SergeyBalabaev / Elective-C-Programming-Language
  Материалы по курсу Углубленное изучение языка С (факультатив) для студентов МИЭТ
  ☆12Updated 7 months ago
• serge0699 / verif_elective_miet
  Репозиторий факультатива по функциональной верификации НИУ МИЭТ
  ☆13Updated last year
• zhelnio / schoolRISCV
  CPU microarchitecture, step by step
  ☆181Updated 3 years ago
• NickolayTernovoy / risc-v_awesome_list
  ☆48Updated 3 years ago
• yathAg / openroad_vsd_7nmContest
  ☆15Updated 2 years ago
• RomeoMe5 / DDLM
  Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
  ☆60Updated 2 years ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆65Updated 3 years ago
• yuri-panchul / basics-graphics-music
  FPGA exercise for beginners
  ☆127Updated this week
• Khalique13 / dvsd_pe_sky130
  This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…
  ☆14Updated 3 years ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆116Updated last year
• raysalemi / Python4RTLVerification
  ☆165Updated 3 years ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆164Updated 3 weeks ago
• mxg / topaz
  ☆24Updated last year
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆127Updated 3 months ago
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆82Updated last year
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆74Updated 4 years ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆97Updated 2 months ago
• wallento / cocotbext-wishbone
  ☆14Updated 9 months ago
• lowRISC / ariane-ethernet
  open-source Ethenet media access controller for Ariane on Genesys-2
  ☆19Updated 6 years ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆144Updated this week
• kunalg123 / vsdflow
  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…
  ☆163Updated 2 years ago