Alternatives and similar repositories for awesome-functional-verification

Users that are interested in awesome-functional-verification are comparing it to the libraries listed below

• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆46Updated 2 months ago
• serge0699 / synth_school_verif_tasks
  Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем
  ☆21Updated 9 months ago
• chipdesignschool / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆55Updated last month
• MPSU / MIRISCV
  Открытое RISC-V процессорное ядро MIRISCV для образовательных целей
  ☆23Updated last year
• yuri-panchul / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆138Updated last month
• vlsiexcellence / Static-Timing-Analysis-Full-Course
  Static Timing Analysis Full Course
  ☆63Updated 3 years ago
• FPGA-Systems / fpga-awesome-list
  Полезные ресурсы по тематике FPGA / ПЛИС
  ☆176Updated 2 months ago
• chipdesignschool / basics-graphics-music
  FPGA exercise for beginners
  ☆43Updated 3 months ago
• serge0699 / verif_elective_miet
  Репозиторий факультатива по функциональной верификации НИУ МИЭТ
  ☆13Updated last year
• yuri-panchul / basics-graphics-music
  FPGA exercise for beginners
  ☆154Updated this week
• RomeoMe5 / DDLM
  Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
  ☆62Updated 2 years ago
• FPGA-InsideOut / hdlgadgets
  human-in-the-loop HDL training tool
  ☆40Updated last year
• zhelnio / schoolRISCV
  CPU microarchitecture, step by step
  ☆186Updated 3 years ago
• NickolayTernovoy / risc-v_awesome_list
  ☆48Updated 4 years ago
• raysalemi / Python4RTLVerification
  ☆174Updated 3 years ago
• lowRISC / ariane-ethernet
  open-source Ethenet media access controller for Ariane on Genesys-2
  ☆19Updated 6 years ago
• SergeyBalabaev / Elective-C-Programming-Language
  Материалы по курсу Углубленное изучение языка С (факультатив) для студентов МИЭТ
  ☆12Updated 11 months ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆57Updated 6 years ago
• kunalg123 / vsdflow
  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…
  ☆163Updated 2 years ago
• MPSU / exAPS
  Архитектуры процессорных систем (старый репозиторий, ранее размещавшийся по адресу github.com/MPSU/APS)
  ☆95Updated last year
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆118Updated 3 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆128Updated 7 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆166Updated last month
• verilator / verilator-announce
  Announcements related to Verilator
  ☆43Updated 2 months ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆195Updated this week
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆130Updated 2 years ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆72Updated 3 years ago
• svunit / svunit
  ☆208Updated 10 months ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆72Updated 3 months ago
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆101Updated last year