esynr3z / adc-evalLinks
📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC
☆22Updated 2 years ago
Alternatives and similar repositories for adc-eval
Users that are interested in adc-eval are comparing it to the libraries listed below
Sorting:
- Time to Digital Converter (TDC)☆35Updated 4 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆46Updated 4 years ago
- A current mode buck converter on the SKY130 PDK☆34Updated 4 years ago
- ☆30Updated 4 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- Small footprint and configurable JESD204B core☆49Updated last month
- converts ValueChangeDump-Files (vcd) to tikz-timing-diagrams☆16Updated 4 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Python script to transform a VCD file to wavedrom format☆81Updated 3 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆46Updated this week
- Efabless mpw7 submission☆13Updated last year
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆66Updated last week
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆38Updated 4 years ago
- Drawio => VHDL and Verilog☆61Updated 2 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆11Updated this week
- general-cores☆21Updated 4 months ago
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆20Updated 4 years ago
- SAR ADC on tiny tapeout☆43Updated 10 months ago
- A flexible and scalable development platform for modern FPGA projects.☆38Updated 2 weeks ago
- ☆33Updated 2 years ago
- An open-source HDL register code generator fast enough to run in real time.☆76Updated last week
- Extensible FPGA control platform☆61Updated 2 years ago
- Library of reusable VHDL components☆28Updated last year
- A mixed-signal system on chip for nanopore-based DNA sequencing☆37Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆40Updated last week
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆30Updated 10 months ago
- JESD204B core for Migen/MiSoC☆35Updated 4 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year