esynr3z / adc-evalLinks
📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC
☆21Updated 2 years ago
Alternatives and similar repositories for adc-eval
Users that are interested in adc-eval are comparing it to the libraries listed below
Sorting:
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated this week
- A current mode buck converter on the SKY130 PDK☆31Updated 4 years ago
- A flexible and scalable development platform for modern FPGA projects.☆37Updated last week
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- general-cores☆21Updated 3 months ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆46Updated 4 years ago
- Time to Digital Converter (TDC)☆35Updated 4 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆18Updated 6 months ago
- USB Full Speed PHY☆46Updated 5 years ago
- Triple Modular Redundancy☆27Updated 6 years ago
- Small footprint and configurable JESD204B core☆47Updated last week
- ☆30Updated 4 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- A padring generator for ASICs☆25Updated 2 years ago
- SAR ADC on tiny tapeout☆43Updated 8 months ago
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆66Updated 2 weeks ago
- Extensible FPGA control platform☆61Updated 2 years ago
- Python script to transform a VCD file to wavedrom format☆81Updated 3 years ago
- Drawio => VHDL and Verilog☆61Updated 2 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆36Updated 4 years ago
- ULPI Link Wrapper (USB Phy Interface)☆30Updated 5 years ago
- VHDL PCIe Transceiver☆31Updated 5 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆38Updated this week
- LMAC Core1 - Ethernet 1G/100M/10M☆18Updated 2 years ago
- A mixed-signal system on chip for nanopore-based DNA sequencing☆34Updated 2 years ago
- Efabless mpw7 submission☆13Updated last year
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆30Updated 9 months ago
- Hardware Design Tool - Mixed Signal Simulation with Verilog☆87Updated 10 months ago