Youssefmdany / RISC-V-Single-Cycle-Processor-Integrated-With-a-Cache-Memory-System-From-RTL-To-GDSView on GitHub
RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS
☆12Aug 26, 2024Updated last year
Alternatives and similar repositories for RISC-V-Single-Cycle-Processor-Integrated-With-a-Cache-Memory-System-From-RTL-To-GDS
Users that are interested in RISC-V-Single-Cycle-Processor-Integrated-With-a-Cache-Memory-System-From-RTL-To-GDS are comparing it to the libraries listed below
Sorting:
- Design and UVM-TB of RISC -V Microprocessor☆34Jun 27, 2024Updated last year
- Design and UVM Verification of an ALU☆10Jun 14, 2024Updated last year
- Motion Estimation implementation by using Verilog HDL☆13Jun 17, 2024Updated last year
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆18Aug 19, 2024Updated last year
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Jan 4, 2025Updated last year
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆28Jun 22, 2024Updated last year
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆49Updated this week
- PQR5ASM is a RISC-V Assembler compliant with RV32I☆19Apr 18, 2025Updated 10 months ago
- ☆13Mar 25, 2022Updated 3 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆34Jun 22, 2024Updated last year
- 基于易灵思Ti60F225开发板和MT9M001双目摄像头，使用Verilog语言完成的双目拼接项目。摄像头输入图像数据后，在使用FAST计算图像特征点的同时，构建滑动窗口计算图像各个像素点的BRIEF描述符，完成后根据BRIEF描述符对两幅图像上的特征点进行暴力匹配，最后…☆20Apr 16, 2025Updated 10 months ago
- A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement,…☆15Nov 24, 2025Updated 3 months ago
- This repo provide an index of VLSI content creators and their materials☆167Aug 21, 2024Updated last year
- A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines☆11Nov 28, 2019Updated 6 years ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆21Jul 7, 2024Updated last year
- 大三上做的本科毕设，包含BNN的替代梯度训练，verilog电路实现，完成180nm工艺流片。☆21Jun 30, 2025Updated 8 months ago
- Dual-core 16-bit RISC processor☆12Jul 21, 2024Updated last year
- Source code & scripts for experimental characterization and demonstration of 1) simultaneous many-row activation, 2) up to nine-input maj…☆11May 17, 2024Updated last year
- ☆11Nov 17, 2025Updated 3 months ago
- UART cocotb module☆11Jun 30, 2021Updated 4 years ago
- ☆11May 30, 2024Updated last year
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆17Nov 11, 2025Updated 3 months ago
- Synthesizable SystemVerilog IP-Core of the I2S Receiver☆10Jun 7, 2020Updated 5 years ago
- Tcl examples repository designed primarily for use with the latest version of the Libero® SoC Design Suite.☆11Jul 18, 2024Updated last year
- Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.☆18Feb 24, 2026Updated last week
- Perceptron-based branch predictor written in C++☆12Dec 14, 2016Updated 9 years ago
- Wishbone to ARM AMBA 4 AXI☆16May 25, 2019Updated 6 years ago
- ☆14Sep 16, 2022Updated 3 years ago
- NTU Computer Architecture 2021 - CPU with Single issue, L1-cache☆11Jan 24, 2022Updated 4 years ago
- RISCulator is a RISC-V emulator.☆12Aug 18, 2023Updated 2 years ago
- A custom single-channel EEG device from PCB design to real-time brainwave visualization. Features analog front-end filtering, STM32 DSP (…☆34Sep 18, 2025Updated 5 months ago
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Jun 5, 2017Updated 8 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆13Nov 12, 2025Updated 3 months ago
- RV32I Implementation on TangNano9K☆11Dec 24, 2022Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆51Jan 4, 2022Updated 4 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆120Dec 17, 2023Updated 2 years ago
- Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research☆17Jan 21, 2024Updated 2 years ago
- Software-based rasterization library☆11Jan 30, 2023Updated 3 years ago