brabect1 / sta_basics_course
Introductory course into static timing analysis (STA).
☆65Updated 2 weeks ago
Related projects ⓘ
Alternatives and complementary repositories for sta_basics_course
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆50Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆63Updated 3 years ago
- ☆52Updated last year
- ☆39Updated 2 years ago
- This is a tutorial on standard digital design flow☆73Updated 3 years ago
- reference block design for the ASAP7nm library in Cadence Innovus☆32Updated 4 months ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆24Updated 3 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆42Updated 3 years ago
- ☆100Updated 4 months ago
- Static Timing Analysis Full Course☆43Updated last year
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆34Updated 2 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆63Updated 3 years ago
- This is the repository for the IEEE version of the book☆49Updated 4 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆37Updated 3 years ago
- Python Tool for UVM Testbench Generation☆48Updated 6 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆58Updated last month
- fakeram generator for use by researchers who do not have access to commercial ram generators☆33Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆45Updated 7 months ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆151Updated 4 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆56Updated 3 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆28Updated 4 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆64Updated 2 years ago
- Xilinx AXI VIP example of use☆32Updated 3 years ago
- ideas and eda software for vlsi design☆47Updated this week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆146Updated this week
- AMC: Asynchronous Memory Compiler☆46Updated 4 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆55Updated last year
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆23Updated 2 years ago
- A complete open-source design-for-testing (DFT) Solution☆136Updated 2 weeks ago
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆18Updated 6 years ago