Alternatives and similar repositories for sta_basics_course

Users that are interested in sta_basics_course are comparing it to the libraries listed below

• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆179Updated 11 months ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆79Updated 4 years ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆63Updated last year
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆70Updated 4 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated last week
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆79Updated 4 years ago
• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆74Updated 4 years ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆67Updated 3 years ago
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆191Updated 5 years ago
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆89Updated last year
• vlsiexcellence / Static-Timing-Analysis-Full-Course
  Static Timing Analysis Full Course
  ☆62Updated 2 years ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆164Updated last month
• raysalemi / Python4RTLVerification
  ☆166Updated 3 years ago
• A-T-Kristensen / simple-alu-uvm
  This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit
  ☆25Updated 7 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆60Updated last year
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆127Updated last month
• vsdip / vsdsram_sky130
  ☆43Updated 3 years ago
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆111Updated 2 years ago
• chipsalliance / uvm-verilator
  ☆99Updated 2 years ago
• ncsu-eda / FreePDK3
  ☆178Updated 4 years ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆99Updated 3 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆72Updated 10 months ago
• ShonTaware / OpenSource_Physical_Design
  This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK
  ☆43Updated 3 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆192Updated 3 years ago
• shariethernet / Physical-Design-with-OpenLANE-using-SKY130-PDK
  This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…
  ☆50Updated 4 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆142Updated 2 weeks ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆54Updated last year
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆132Updated 7 years ago
• The-OpenROAD-Project / asap7
  ☆201Updated 7 months ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago