brabect1 / sta_basics_course
Introductory course into static timing analysis (STA).
☆63Updated last week
Related projects ⓘ
Alternatives and complementary repositories for sta_basics_course
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆63Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆62Updated 3 years ago
- ☆39Updated 2 years ago
- Static Timing Analysis Full Course☆43Updated last year
- This is a tutorial on standard digital design flow☆72Updated 3 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆48Updated 2 years ago
- This is the repository for the IEEE version of the book☆49Updated 4 years ago
- ☆52Updated last year
- Python Tool for UVM Testbench Generation☆49Updated 5 months ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆55Updated last year
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆34Updated 2 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆24Updated 3 years ago
- ☆97Updated 3 months ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆42Updated 3 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆41Updated 7 months ago
- General Purpose AXI Direct Memory Access☆44Updated 5 months ago
- EE 260 Winter 2017: Advanced VLSI Design☆58Updated 7 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆27Updated 2 years ago
- ☆73Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆140Updated last year
- Python packages providing a library for Verification Stimulus and Coverage☆113Updated last month
- ideas and eda software for vlsi design☆47Updated last week
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆45Updated 6 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆56Updated 3 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆36Updated 3 years ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆52Updated 3 months ago
- A Fast, Low-Overhead On-chip Network☆134Updated 2 weeks ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆43Updated 3 years ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆44Updated 8 years ago