Alternatives and similar repositories for Study-materials

Users that are interested in Study-materials are comparing it to the libraries listed below

• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆59Updated 3 years ago
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 5 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆35Updated 6 years ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• ConstantPark / Neural-Network-Acceleration-2
  Neural Network Acceleration using CPU/GPU, ASIC, FPGA
  ☆63Updated 5 years ago
• kmisimn76 / SparseAccel
  CNN simd based accelerator using Vitis HLS
  ☆10Updated 3 years ago
• sherylll / lenet5-accelerator
  FPGA and GPU acceleration of LeNet5
  ☆34Updated 6 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• ConstantPark / Nerual-Network-Acceleration-1
  Neural Network Acceleration such as ASIC, FPGA, GPU, and PIM
  ☆54Updated 5 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆70Updated 6 years ago
• hyoukjun / MAESTRO
  MAESTRO binary release
  ☆22Updated 5 years ago
• hyoukjun / DesignCNNAccelerators
  Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
  ☆31Updated 7 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆54Updated 4 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆27Updated 4 years ago
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆38Updated 5 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 5 years ago
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆12Updated 5 years ago
• onioncc / iSmartDNN
  Light-weighted neural network inference for object detection on small-scale FPGA board
  ☆93Updated 6 years ago
• Yang-YiFan / DiracDeltaNet
  PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
  ☆32Updated 6 years ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆48Updated 5 years ago
• lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS
  This project implements a convolution kernel based on vivado HLS on zcu104
  ☆37Updated 5 years ago
• maeri-project / MAERI_bsv_isca2018
  MAERI public release
  ☆31Updated 4 years ago
• ehw-fit / evoapproxlib
  Library of approximate arithmetic circuits
  ☆56Updated 3 years ago
• isuckatdrifting / Zeus
  NVDLA small config implementation on Zynq ZCU104 (evaluation)
  ☆24Updated 6 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆49Updated 7 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆26Updated 6 years ago
• hyoukjun / microswitch-noc
  ☆27Updated 6 years ago
• eda-lab / CNNAF-CNN-Accelerator
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆10Updated 3 years ago
• nqHITSZ / Systolic-Array
  course design
  ☆23Updated 7 years ago