kim-sunghoon / Study-materials

Related projects ⓘ

Alternatives and complementary repositories for Study-materials

• ConstantPark / Nerual-Network-Acceleration-1
  Neural Network Acceleration such as ASIC, FPGA, GPU, and PIM
  ☆51Updated 4 years ago
• maeri-project / MAERI_bsv_isca2018
  MAERI public release
  ☆31Updated 3 years ago
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• Yang-YiFan / DiracDeltaNet
  PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
  ☆31Updated 5 years ago
• hyoukjun / DesignCNNAccelerators
  Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
  ☆25Updated 6 years ago
• ConstantPark / Neural-Network-Acceleration-2
  Neural Network Acceleration using CPU/GPU, ASIC, FPGA
  ☆60Updated 4 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆51Updated 2 years ago
• yonseicasl / NeuroSpector
  NeuroSpector: Dataflow and Mapping Optimization of Deep Neural Network Accelerators
  ☆17Updated this week
• PolyArch / fp-diannao
  ☆14Updated last year
• lite-david / comet
  RISC-V ISA based 32-bit processor written in HLS
  ☆15Updated 5 years ago
• xupgit / System-Design-on-Zynq-using-SDSoC
  ☆8Updated 5 years ago
• cornell-brg / pymtl-tut-hls
  Tutorial for integrating PyMTL and Vivado HLS
  ☆17Updated 8 years ago
• GATECH-EIC / AutoDNNchip
  ☆69Updated 4 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆59Updated 3 years ago
• ahirsharan / LSTM
  Single Long Short Term Memory (LSTM) cell : Verilog Implementation
  ☆29Updated 4 years ago
• maao666 / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆24Updated 3 years ago
• awai54st / LUTNet
  ☆55Updated 4 years ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆86Updated 4 years ago
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆10Updated 4 years ago
• thousrm / universal_NPU-CNN_accelerator
  hardware design of universal NPU(CNN accelerator) for various convolution neural network
  ☆71Updated last week
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆48Updated 3 years ago
• hyoukjun / MAESTRO
  MAESTRO binary release
  ☆22Updated 4 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 3 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆32Updated 5 years ago
• ehw-fit / tf-approximate
  Approximate layers - TensorFlow extension
  ☆26Updated 6 months ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆42Updated 2 years ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆43Updated last year
• ucb-bar / gemmini-rocc-tests
  Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
  ☆52Updated this week
• ZigZag-Project / zigzag-v1
  A Fast DNN Accelerator Design Space Exploration Framework.
  ☆45Updated 2 years ago