Alternatives and similar repositories for Study-materials:

Users that are interested in Study-materials are comparing it to the libraries listed below

• ConstantPark / Nerual-Network-Acceleration-1
  Neural Network Acceleration such as ASIC, FPGA, GPU, and PIM
  ☆51Updated 4 years ago
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• maeri-project / MAERI_bsv_isca2018
  MAERI public release
  ☆31Updated 3 years ago
• ConstantPark / Neural-Network-Acceleration-2
  Neural Network Acceleration using CPU/GPU, ASIC, FPGA
  ☆60Updated 4 years ago
• hyoukjun / DesignCNNAccelerators
  Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
  ☆27Updated 6 years ago
• g0kul / vcnn
  Verilog Convolutional Neural Network on PYNQ
  ☆28Updated 6 years ago
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆25Updated 4 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 3 years ago
• Yang-YiFan / DiracDeltaNet
  PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
  ☆31Updated 5 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆42Updated last month
• cornell-brg / pymtl-tut-hls
  Tutorial for integrating PyMTL and Vivado HLS
  ☆18Updated 8 years ago
• ucb-bar / gemmini-rocc-tests
  Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
  ☆55Updated last month
• hyoukjun / MAESTRO
  MAESTRO binary release
  ☆22Updated 5 years ago
• yonseicasl / NeuroSpector
  NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators
  ☆20Updated last week
• lukasc-ch / ExtendedBitPlaneCompression
  Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…
  ☆17Updated 5 years ago
• GATECH-EIC / AutoDNNchip
  ☆70Updated 5 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• nqHITSZ / Systolic-Array
  course design
  ☆22Updated 7 years ago
• awai54st / LUTNet
  ☆57Updated 4 years ago
• kkiningh / cs231n-project
  CNN accelerator
  ☆28Updated 7 years ago
• PSCLab-ASU / Systolic-CNN
  ☆15Updated 4 years ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆36Updated 5 years ago
• lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS
  This project implements a convolution kernel based on vivado HLS on zcu104
  ☆37Updated 5 years ago
• neurosim / DNN_NeuroSim_V1.2
  Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
  ☆8Updated 3 years ago
• PolyArch / fp-diannao
  ☆14Updated last year
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• VeriGOOD-ML / public
  ☆57Updated last year
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 2 years ago
• ARM-software / DeepFreeze
  ☆40Updated 5 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆57Updated 3 years ago