🌊 CLI tool for RTL waveform (VCD/FST/FSDB) inspection
☆55Aug 23, 2026Updated this week
Alternatives and similar repositories for wavepeek
Users that are interested in wavepeek are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Project PLS is developed based on icarus iverilog and will compile verilog into a much faster optimized model.☆13Nov 15, 2021Updated 4 years ago
- Verilog (SystemVerilog) coding style☆42Jan 7, 2019Updated 7 years ago
- Репозиторий факультатива по функциональной верификации НИУ МИЭТ☆19Aug 24, 2024Updated 2 years ago
- 太原理工大学先进计算机系统研究实验室（“一生一芯”工作室）辅助教学使用的前置知识讲义☆17Aug 7, 2026Updated 2 weeks ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆35Feb 2, 2026Updated 6 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Basic chisel difftest environment for RTL design (WIP☆21Mar 8, 2025Updated last year
- ☆11Jul 12, 2023Updated 3 years ago
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆76Updated this week
- Quadrature sampling down converter software defined radio☆19Jun 11, 2021Updated 5 years ago
- Contains source code for sin/cos table verification using UVM☆23Mar 9, 2021Updated 5 years ago
- Contract-Aware RTL Code Generation Agents with Temporal Tracing, Slicing and Formal Verification☆24Jan 28, 2026Updated 6 months ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆45May 5, 2023Updated 3 years ago
- The Scala parser to parse riscv/riscv-opcodes generate☆26Jan 21, 2026Updated 7 months ago
- Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.☆20Jul 29, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SystemVerilog synthesis tool☆235Mar 10, 2025Updated last year
- Методические материалы курса "Практикум по ПЛИС"☆51May 29, 2026Updated 2 months ago
- Example of Python and PyTest powered workflow for a HDL simulation☆15Jan 17, 2021Updated 5 years ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆24Mar 31, 2026Updated 4 months ago
- Craft your EDA toolchain with GRH IR☆19Updated this week
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆29Jan 2, 2025Updated last year
- SystemVerilog Linter based on pyslang☆33May 5, 2025Updated last year
- Материалы по курсу Углубленное изучение языка С (факультатив) для студентов МИЭТ☆12Feb 4, 2025Updated last year
- Nix template for the chisel-based industrial designing flows.☆58Jul 21, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆49Nov 9, 2021Updated 4 years ago
- ☆21May 26, 2025Updated last year
- pcie datalink layer implementation in verilog/systemverilog☆16May 22, 2026Updated 3 months ago
- Generate bitstream from FPGA assembly.☆28Aug 11, 2026Updated 2 weeks ago
- A Python package for creating and solving constrained randomization problems.☆19Aug 10, 2026Updated 2 weeks ago
- Static Timing Analysis Full Course☆76Jan 14, 2023Updated 3 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆43Updated this week
- Summary of bugs in Xuantie C9XX core design. include C906/C908/C910/C920☆36Jun 1, 2026Updated 2 months ago
- A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.☆14Nov 23, 2022Updated 3 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- CIRCT and Yosys interoperability, demonstrated with CHISEL☆18Feb 3, 2026Updated 6 months ago
- BYU Pynq PR Video Pipeline Hardware☆13Oct 2, 2025Updated 10 months ago
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆24Sep 19, 2023Updated 2 years ago
- ☆16Aug 26, 2025Updated last year
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆25May 8, 2020Updated 6 years ago
- Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"☆53May 16, 2026Updated 3 months ago
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆13Aug 14, 2020Updated 6 years ago