Repository gathering basic modules for CDC purpose
☆63Dec 31, 2019Updated 6 years ago
Alternatives and similar repositories for cdc
Users that are interested in cdc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Contains source code for sin/cos table verification using UVM☆23Mar 9, 2021Updated 5 years ago
- ☆25May 20, 2020Updated 6 years ago
- Example files for the book FPGA SIMULATION☆23Apr 6, 2017Updated 9 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- SystemVerilog Logger☆19Apr 6, 2026Updated 6 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 8 years ago
- USB -> AXI Debug Bridge☆47Jun 5, 2021Updated 5 years ago
- MIPSfpga+ allows loading programs via UART and has a switchable clock☆113Jun 27, 2019Updated 7 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆484Sep 3, 2026Updated last month
- Generic AXI master stub☆20Jul 17, 2014Updated 12 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Mar 6, 2018Updated 8 years ago
- Common SystemVerilog components☆807Sep 18, 2026Updated 3 weeks ago
- Mastering FPGASIC Book☆19Oct 26, 2025Updated 11 months ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- 5 days (30 hours) is all what took me to learn the basics and design a pipelined RV32I core. Check this article to know more !☆14Feb 2, 2022Updated 4 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 11 years ago
- ☆27Jun 12, 2022Updated 4 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 10 years ago
- datasheet generator☆31Sep 10, 2026Updated last month
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆37Mar 13, 2025Updated last year
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆50May 10, 2024Updated 2 years ago
- A cross platform, formally verified, open source, hyperRAM controller with simulator☆17Feb 22, 2019Updated 7 years ago
- System Verilog and Emulation. Written all the five channels.☆36Mar 9, 2017Updated 9 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆43Jun 14, 2018Updated 8 years ago
- Parametric AXI4 crossbar in SystemVerilog☆247May 25, 2026Updated 4 months ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆12Sep 23, 2022Updated 4 years ago
- A small RISC-V core (SystemVerilog)☆33Aug 26, 2019Updated 7 years ago
- BlackParrot on Zynq☆56Jun 17, 2026Updated 3 months ago
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆31Oct 28, 2018Updated 7 years ago
- 学习AXI接口，以及xilinx DDR3 IP使用☆40Mar 6, 2017Updated 9 years ago
- cryptography ip-cores in vhdl / verilog☆42Feb 20, 2021Updated 5 years ago
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆18Apr 12, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Static Timing Analysis Full Course☆76Jan 14, 2023Updated 3 years ago
- Verilog Configurable Cache☆197Sep 21, 2026Updated 2 weeks ago
- Xilinx AXI VIP example of use☆46Apr 24, 2021Updated 5 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆136Feb 11, 2021Updated 5 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆42Dec 2, 2018Updated 7 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆25May 8, 2020Updated 6 years ago
- River Raid game on FPGA☆23Oct 30, 2016Updated 9 years ago