Repository gathering basic modules for CDC purpose
☆58Dec 31, 2019Updated 6 years ago
Alternatives and similar repositories for cdc
Users that are interested in cdc are comparing it to the libraries listed below
Sorting:
- Contains source code for sin/cos table verification using UVM☆21Mar 9, 2021Updated 4 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- ☆25May 20, 2020Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Oct 16, 2017Updated 8 years ago
- SystemVerilog Logger☆19Sep 30, 2025Updated 5 months ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- Generic AXI master stub☆19Jul 17, 2014Updated 11 years ago
- USB -> AXI Debug Bridge☆42Jun 5, 2021Updated 4 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆48May 10, 2024Updated last year
- Example files for the book FPGA SIMULATION☆23Apr 6, 2017Updated 8 years ago
- ☆27Jun 12, 2022Updated 3 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Mar 6, 2018Updated 7 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆39Dec 2, 2018Updated 7 years ago
- Xilinx AXI VIP example of use☆43Apr 24, 2021Updated 4 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆423Feb 13, 2026Updated 2 weeks ago
- BlackParrot on Zynq☆50Feb 11, 2026Updated 2 weeks ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆17Sep 2, 2023Updated 2 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 9 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆40Mar 6, 2017Updated 8 years ago
- MIPSfpga+ allows loading programs via UART and has a switchable clock☆112Jun 27, 2019Updated 6 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆21Feb 4, 2025Updated last year
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆17Apr 12, 2020Updated 5 years ago
- Common SystemVerilog components☆713Updated this week
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆20May 4, 2017Updated 8 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 5 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆212Sep 2, 2025Updated 5 months ago
- Mastering FPGASIC Book☆18Oct 26, 2025Updated 4 months ago
- System Verilog and Emulation. Written all the five channels.☆35Mar 9, 2017Updated 8 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Dec 24, 2024Updated last year
- FPU Generator☆20Jul 19, 2021Updated 4 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆24May 8, 2020Updated 5 years ago
- Collection of IPs based on AMBA (AHB, APB, AXI) protocols☆19Feb 1, 2017Updated 9 years ago
- MMC (and derivative standards) host controller☆25Sep 14, 2020Updated 5 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- Static Timing Analysis Full Course☆64Jan 14, 2023Updated 3 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆24Nov 7, 2018Updated 7 years ago