Alternatives and similar repositories for APB-Protocol

Users that are interested in APB-Protocol are comparing it to the libraries listed below

• Anjali-287 / SPI-Interface
  UVM Testbench to verify serial transmission of data between SPI master and slave
  ☆50Updated 5 years ago
• rpjayaraman / DV-resource
  A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.
  ☆24Updated 2 weeks ago
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆97Updated 2 years ago
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆31Updated 5 years ago
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆32Updated last year
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆65Updated 2 years ago
• Artityagi123456789 / -100dasofSystemVerilog
  System Verilog using Functional Verification
  ☆12Updated last year
• techvinodreddy / UART-IP-CORE16550A-Verification-UVM
  The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …
  ☆17Updated 4 years ago
• deekshithkrishnegowda / AHB2APB-bridge-IP-core-verification
  Maven Silicon Project
  ☆19Updated 6 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆69Updated 4 years ago
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆64Updated last year
• amiq-consulting / amiq_apb
  SystemVerilog VIP for AMBA APB protocol
  ☆79Updated 3 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆148Updated 3 years ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆24Updated 2 years ago
• Noman-10xe / AXI-DMA-Verification
  Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM
  ☆36Updated 2 months ago
• yuravg / uvm_tb_cross_bar
  SystemVerilog UVM testbench example
  ☆34Updated last year
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆26Updated 3 years ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆35Updated 9 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆106Updated 8 months ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆37Updated 5 years ago
• Kholoud-Ebrahim / SPI_Protocol
  UVM based Verification of SPI_Protocol. A Serial intra System Communication Peripheral Protocol.
  ☆10Updated last year
• akzare / Async_FIFO_Verification
  Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.
  ☆55Updated 5 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆79Updated last year
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆143Updated 2 months ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆48Updated 3 years ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆155Updated 5 years ago
• basemhesham / Design-and-ASIC-Implementation-of-UART
  This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…
  ☆21Updated last year
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆126Updated 7 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆49Updated 5 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆35Updated 2 years ago