Motion Estimation implementation by using Verilog HDL
☆13Jun 17, 2024Updated 2 years ago
Alternatives and similar repositories for Motion_Estimation_Hardware_Verilog
Users that are interested in Motion_Estimation_Hardware_Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆13Aug 26, 2024Updated last year
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆44Jun 19, 2024Updated 2 years ago
- ☆22Sep 26, 2025Updated 9 months ago
- OscillatorIMP ecosystem FPGA IP sources☆28Feb 22, 2026Updated 4 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆19Updated this week
- Design of LDO using open source SKY130PDK☆17Aug 24, 2024Updated last year
- Wearanize+ is a multimodal sleep dataset containing overnight sleep data from 130 young, healthy participants using PSG and three wearabl…☆23Jun 7, 2026Updated last month
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆51Dec 3, 2023Updated 2 years ago
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.☆17Mar 26, 2026Updated 3 months ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆13Jul 8, 2019Updated 7 years ago
- An open silicon CHERIoT Ibex microcontroller chip☆18May 23, 2025Updated last year
- [NeurIPS 2024 Spotlight] Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs☆15Feb 22, 2026Updated 4 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆56Jan 4, 2022Updated 4 years ago
- Quad cluster of RISC-V cores with peripherals and local memory☆24Feb 3, 2022Updated 4 years ago
- Tiny Tapeout project build tools + chip integration scripts☆34Jun 15, 2026Updated 3 weeks ago
- Low Power VLSI Design Concepts & Interview Questions for Top Semiconductor MNCs☆11Jan 12, 2023Updated 3 years ago
- Design and UVM-TB of RISC -V Microprocessor☆34Jun 27, 2024Updated 2 years ago
- ☆93Jun 29, 2026Updated last week
- Academic project for the course of Digital Systems Design. The aim of the project was to design and implement an IIR audio filter on FPGA☆12Mar 29, 2018Updated 8 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 5 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆122Jul 9, 2023Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆16Mar 17, 2019Updated 7 years ago
- ☆11Nov 17, 2025Updated 7 months ago
- A scheduler to manage a multi tool dual arm robot while avoiding arm-to-arm collisions; considering complex side constraints; and optimiz…☆11Jul 6, 2021Updated 5 years ago
- A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement,…☆16Mar 8, 2026Updated 4 months ago
- TinyTapeout-02 submission repository☆29Mar 27, 2024Updated 2 years ago
- Dr Sparsh's lecture slides on RISC-V ISA☆22Jun 9, 2025Updated last year
- ☆56Jun 19, 2021Updated 5 years ago
- This project presents a novel approach for J peak detection in Heart-Rate monitoring. The proposed approach employs accelerometers to col…☆10Oct 30, 2023Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- DeviceIO是一个驱动框架,用于封装嵌入式HAL驱动,为上层应用提供服务。☆10Jun 1, 2024Updated 2 years ago
- ☆10Feb 16, 2025Updated last year
- ARTICo³ - Dynamic and Partially Reconfigurable Architecture for Run-Time Adaptive, High Performance Embedded Computing☆12Sep 10, 2024Updated last year
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- NeuroRVQ: Multi-Scale Biosignal Tokenization for Generative Foundation Models☆49Jun 30, 2026Updated last week
- Physics-Informed Neural Networks for Cardiovascular Blood Flow Simulations☆24Apr 7, 2025Updated last year
- Class project for COMP-781, Robotics. This is a CUDA-based collision detector for motion planning.☆13Apr 29, 2019Updated 7 years ago