FPGA-Systems / fpga-awesome-listLinks
Полезные ресурсы по тематике FPGA / ПЛИС
☆176Updated 2 months ago
Alternatives and similar repositories for fpga-awesome-list
Users that are interested in fpga-awesome-list are comparing it to the libraries listed below
Sorting:
- Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"☆46Updated last month
- FPGA exercise for beginners☆152Updated this week
- SystemVerilog language-oriented exercises☆136Updated last week
- Control and Status Register map generator for HDL projects☆128Updated 7 months ago
- CPU microarchitecture, step by step☆185Updated 3 years ago
- SystemVerilog language-oriented exercises☆54Updated 2 weeks ago
- ☆48Updated 4 years ago
- Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем☆21Updated 8 months ago
- FPGA Logic Analyzer and GUI☆145Updated 3 years ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆193Updated 3 weeks ago
- Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)☆62Updated 2 years ago
- open-source SDKs for the SCR1 core☆76Updated last year
- ☆45Updated 3 months ago
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆163Updated 4 years ago
- Verilog digital signal processing components☆163Updated 3 years ago
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆23Updated last year
- human-in-the-loop HDL training tool☆39Updated last year
- Verilog UART☆187Updated 12 years ago
- ☆76Updated 3 years ago
- ☆114Updated 2 years ago
- A simple implementation of a UART modem in Verilog.☆168Updated 4 years ago
- DigitalDesignSchool2022/23 repository☆21Updated 3 years ago
- A huge VHDL library for FPGA and digital ASIC development☆417Updated 2 weeks ago
- Many peripherals in Verilog ready to use☆40Updated last year
- A set of Wishbone Controlled SPI Flash Controllers☆93Updated 3 years ago
- ChipEXPO 2020 Digital Design School Labs☆37Updated 3 years ago
- Flexible VHDL library☆191Updated 2 years ago
- A full-speed device-side USB peripheral core written in Verilog.☆235Updated 3 years ago
- Simple 8-bit UART realization on Verilog HDL.☆111Updated last year
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆81Updated 2 years ago