Alternatives and similar repositories for fpga-awesome-list

Users that are interested in fpga-awesome-list are comparing it to the libraries listed below

• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆45Updated last week
• yuri-panchul / basics-graphics-music
  FPGA exercise for beginners
  ☆143Updated this week
• yuri-panchul / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆132Updated 2 weeks ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆128Updated 5 months ago
• NickolayTernovoy / risc-v_awesome_list
  ☆48Updated 4 years ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆186Updated 3 weeks ago
• serge0699 / synth_school_verif_tasks
  Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем
  ☆22Updated 7 months ago
• zhelnio / schoolRISCV
  CPU microarchitecture, step by step
  ☆183Updated 3 years ago
• chipdesignschool / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆52Updated 2 weeks ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆155Updated 4 years ago
• fpgacademy / DESim
  ☆44Updated last month
• HDLForBeginners / Examples
  ☆110Updated 2 years ago
• lekgolo167 / enxor-logic-analyzer
  FPGA Logic Analyzer and GUI
  ☆143Updated 2 years ago
• RomeoMe5 / DDLM
  Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
  ☆61Updated 2 years ago
• syntacore / scr1-sdk
  open-source SDKs for the SCR1 core
  ☆76Updated last year
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆61Updated 2 years ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆411Updated this week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆148Updated 5 months ago
• DigitalDesignSchool / ce2020labs
  ChipEXPO 2020 Digital Design School Labs
  ☆37Updated 3 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆91Updated 3 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆164Updated 4 years ago
• MPSU / MIRISCV
  Открытое RISC-V процессорное ядро MIRISCV для образовательных целей
  ☆23Updated 11 months ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆110Updated last year
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆159Updated 3 years ago
• robseb / rsyocto
  🤖 SoCFPGA: Open-Source Embedded Linux Distribution with a highly flexible build system, developed for Intel (ALTERA) SoC-FPGAs (Cyclone …
  ☆114Updated 4 years ago
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆191Updated 2 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆316Updated last year
• hypernyan / eth_vlg
  ☆74Updated 3 years ago
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆185Updated last year
• FPGA-InsideOut / hdlgadgets
  human-in-the-loop HDL training tool
  ☆40Updated last year