Alternatives and similar repositories for fpga-awesome-list

Users that are interested in fpga-awesome-list are comparing it to the libraries listed below

• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆43Updated 2 months ago
• yuri-panchul / basics-graphics-music
  FPGA exercise for beginners
  ☆127Updated this week
• yuri-panchul / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆110Updated 2 months ago
• zhelnio / schoolRISCV
  CPU microarchitecture, step by step
  ☆181Updated 3 years ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆180Updated last week
• chipdesignschool / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆49Updated 2 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆127Updated 3 months ago
• RomeoMe5 / DDLM
  Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
  ☆60Updated 2 years ago
• fpgacademy / DESim
  ☆43Updated 3 months ago
• lekgolo167 / enxor-logic-analyzer
  FPGA Logic Analyzer and GUI
  ☆136Updated 2 years ago
• serge0699 / synth_school_verif_tasks
  Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем
  ☆22Updated 5 months ago
• NickolayTernovoy / risc-v_awesome_list
  ☆48Updated 3 years ago
• syntacore / scr1-sdk
  open-source SDKs for the SCR1 core
  ☆75Updated 10 months ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆396Updated last week
• HDLForBeginners / Examples
  ☆103Updated 2 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 3 months ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆144Updated 4 years ago
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆189Updated 2 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆88Updated 2 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆155Updated 2 years ago
• MPSU / MIRISCV
  Открытое RISC-V процессорное ядро MIRISCV для образовательных целей
  ☆19Updated 9 months ago
• klyone / opencores-ip
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆112Updated 9 years ago
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆158Updated last week
• FPGA-InsideOut / hdlgadgets
  human-in-the-loop HDL training tool
  ☆38Updated last year
• hypernyan / eth_vlg
  ☆74Updated 3 years ago
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆57Updated last year
• jamieiles / uart
  Verilog UART
  ☆180Updated 12 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆155Updated 3 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆73Updated last week
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆309Updated last year