FPGA-Systems / fpga-awesome-list
Полезные ресурсы по тематике FPGA / ПЛИС
☆156Updated 2 weeks ago
Related projects ⓘ
Alternatives and complementary repositories for fpga-awesome-list
- FPGA exercise for beginners☆89Updated this week
- Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"☆32Updated 2 months ago
- SystemVerilog language-oriented exercises☆48Updated 3 weeks ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆108Updated this week
- CPU microarchitecture, step by step☆164Updated 2 years ago
- ☆47Updated 3 years ago
- Control and Status Register map generator for HDL projects☆99Updated this week
- Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем☆14Updated 2 weeks ago
- FPGA Logic Analyzer and GUI☆91Updated last year
- ChipEXPO 2020 Digital Design School Labs☆35Updated 2 years ago
- Исходные коды к главам книги "Цифровой синтез: прак тический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)☆53Updated last year
- DigitalDesignSchool2022/23 repository☆19Updated last year
- ☆79Updated last year
- SystemVerilog language-oriented exercises☆37Updated 3 weeks ago
- Control and status register code generator toolchain☆106Updated 2 months ago
- This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, unde…☆141Updated 4 months ago
- A huge VHDL library for FPGA development☆347Updated this week
- ☆120Updated 2 years ago
- ☆53Updated 2 years ago
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆50Updated 9 years ago
- open-source SDKs for the SCR1 core☆68Updated last week
- This repo provide an index of VLSI content creators and their materials☆136Updated 3 months ago
- Opensource DDR3 Controller☆217Updated this week
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆68Updated 11 months ago
- Verilog digital signal processing components☆108Updated 2 years ago
- Flexible VHDL library☆181Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆54Updated 3 weeks ago
- Basic RISC-V Test SoC☆104Updated 5 years ago
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆11Updated 7 months ago
- Static Timing Analysis Full Course☆43Updated last year