Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
☆47Feb 12, 2026Updated 2 weeks ago
Alternatives and similar repositories for constraints
Users that are interested in constraints are comparing it to the libraries listed below
Sorting:
- Generate symbols from HDL components/modules☆22Feb 6, 2023Updated 3 years ago
- VHDL related news.☆27Updated this week
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 9 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated last year
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Feb 24, 2026Updated last week
- Library of reusable VHDL components☆28Mar 7, 2024Updated last year
- Building and deploying container images for open source electronic design automation (EDA)☆121Oct 3, 2024Updated last year
- Virtual development board for HDL design☆42Mar 31, 2023Updated 2 years ago
- A VHDL Core Library.☆18Mar 29, 2017Updated 8 years ago
- Standard and Curated cores, tested and working.☆11Dec 29, 2022Updated 3 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Feb 16, 2026Updated 2 weeks ago
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 3 years ago
- ulx3s ghdl examples☆15Mar 6, 2021Updated 4 years ago
- JavaScript action for users to easily install tip/nightly GHDL assets in GitHub Actions workflows☆16Jan 12, 2025Updated last year
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 3 years ago
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 5 years ago
- VHDL plugin for RgGen☆15Jan 7, 2026Updated last month
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆13Sep 22, 2025Updated 5 months ago
- Repo to help explain the different options users have for packaging.☆19Jun 8, 2022Updated 3 years ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆51Feb 24, 2026Updated last week
- cryptography ip-cores in vhdl / verilog☆41Feb 20, 2021Updated 5 years ago
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Feb 9, 2026Updated 3 weeks ago
- A curated list of awesome resources for HDL design and verification☆169Updated this week
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆17Nov 16, 2023Updated 2 years ago
- Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.☆10Jul 22, 2020Updated 5 years ago
- vhdl related contents☆11Apr 27, 2020Updated 5 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆52Jun 5, 2022Updated 3 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- Interface definitions for VHDL-2019.☆34Jan 12, 2026Updated last month
- VHDL dependency analyzer☆24Mar 10, 2020Updated 5 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 2 years ago
- Open Source Verification Bundle for VHDL and System Verilog☆48Jan 12, 2024Updated 2 years ago
- ☆33Apr 30, 2023Updated 2 years ago
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆26Sep 16, 2025Updated 5 months ago
- ☆59Jul 4, 2022Updated 3 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics☆14Updated this week