vlsiexcellence / Digital-ASIC-Design-Projects-Links
Verilog Design, Simulation & Synthesis of Digital ASIC Projects
☆17Updated 3 years ago
Alternatives and similar repositories for Digital-ASIC-Design-Projects-
Users that are interested in Digital-ASIC-Design-Projects- are comparing it to the libraries listed below
Sorting:
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Updated 2 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆108Updated 2 years ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆43Updated 5 months ago
- ☆55Updated 4 years ago
- ☆17Updated 2 years ago
- System Verilog using Functional Verification☆12Updated last year
- IEEE Executive project for the year 2021-2022☆10Updated 3 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆19Updated 2 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆46Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆67Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆39Updated 3 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆18Updated last year
- A collection of commonly asked RTL design interview questions☆38Updated 8 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆103Updated last year
- Architectural design of data router in verilog☆32Updated 6 years ago
- Asynchronous fifo in verilog☆38Updated 9 years ago
- Design Verification Engineer interview preparation guide.☆43Updated 6 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆51Updated 4 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Updated 8 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- ☆14Updated 3 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆56Updated 4 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆74Updated 3 years ago
- ☆41Updated 3 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- Static Timing Analysis Full Course☆63Updated 3 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆76Updated 5 years ago
- SystemVerilog UVM testbench example☆37Updated last year
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆74Updated last year