Verilog Design, Simulation & Synthesis of Digital ASIC Projects
☆18Jan 27, 2023Updated 3 years ago
Alternatives and similar repositories for Digital-ASIC-Design-Projects-
Users that are interested in Digital-ASIC-Design-Projects- are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog Fundamentals Explained for Beginners and Professionals☆20Jan 15, 2023Updated 3 years ago
- Single Port RAM, Dual Port RAM, FIFO☆33May 17, 2022Updated 3 years ago
- Project 2.2 Frequency counter☆12May 30, 2025Updated 9 months ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 3 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆111Jul 9, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- System Verilog using Functional Verification☆12Apr 8, 2024Updated last year
- ☆17Feb 16, 2023Updated 3 years ago
- Design and UVM Verification of an ALU☆11Jun 14, 2024Updated last year
- Static Timing Analysis Full Course☆65Jan 14, 2023Updated 3 years ago
- System Verilog BootCamp☆25Jan 21, 2022Updated 4 years ago
- Some beginner projects using verilog HDL, along with some documentation on basic syntax☆13Jun 13, 2021Updated 4 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆12Jul 28, 2021Updated 4 years ago
- Verilog implementation of Pac-Man made for a class's final project☆19Mar 7, 2012Updated 14 years ago
- Go Board FPGA Project for Ambient Light Sensor in VHDL and Verilog☆10Apr 20, 2019Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- The Soldier Health Monitoring and Position Tracking System allows the military personnel to track the current GPS position of a soldier a…☆11Dec 27, 2021Updated 4 years ago
- This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codeba…☆17May 4, 2024Updated last year
- ☆55Jun 19, 2021Updated 4 years ago
- DMA Project using Verilog HDL☆14Dec 26, 2019Updated 6 years ago
- Using an Altera DE10-Lite FPGA development board to simulate an FFT processor. Audio input frequencies will be visualized onto a VGA disp…☆15May 5, 2020Updated 5 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆39Nov 6, 2022Updated 3 years ago
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆25Feb 19, 2025Updated last year
- Integrated Circuit Design - IC Design Flow and Project-Based Learning☆50Mar 1, 2026Updated 3 weeks ago
- Vitis-AI 1.3 TensorFlow2 flow with a custom CNN model, targeted ZCU102 evaluation board.☆15Apr 6, 2021Updated 4 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆10Oct 16, 2023Updated 2 years ago
- The UVM written in Python☆17Dec 26, 2025Updated 3 months ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- Engineering Program on RTL Design for FPGA Accelerator☆33Aug 1, 2020Updated 5 years ago
- APB Timer Unit☆13Oct 30, 2025Updated 4 months ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆21Nov 26, 2018Updated 7 years ago
- Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout☆14May 11, 2014Updated 11 years ago
- This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…☆21Mar 2, 2023Updated 3 years ago
- UART in Verilog and VHDL☆18Aug 21, 2022Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- This repository explores writing cocotb-style tests in modern C++, using coroutines and strong typing, with the goal of maintaining a Pyt…☆28Feb 16, 2026Updated last month
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Dec 8, 2012Updated 13 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆54Updated this week
- Simple single-port AXI memory interface☆49Jun 7, 2024Updated last year
- ☆18Jun 3, 2019Updated 6 years ago
- Submission template for Tiny Tapeout 9 - Verilog HDL Projects☆14Nov 13, 2024Updated last year
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆50Mar 3, 2024Updated 2 years ago