Verilog Design, Simulation & Synthesis of Digital ASIC Projects
☆20Jan 27, 2023Updated 3 years ago
Alternatives and similar repositories for Digital-ASIC-Design-Projects-
Users that are interested in Digital-ASIC-Design-Projects- are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog Fundamentals Explained for Beginners and Professionals☆21Jan 15, 2023Updated 3 years ago
- Low Power VLSI Design Concepts & Interview Questions for Top Semiconductor MNCs☆12Jan 12, 2023Updated 3 years ago
- Single Port RAM, Dual Port RAM, FIFO☆34May 17, 2022Updated 4 years ago
- Project 2.2 Frequency counter☆12May 30, 2025Updated last year
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- System Verilog using Functional Verification☆12Apr 8, 2024Updated 2 years ago
- ☆17Feb 16, 2023Updated 3 years ago
- Design and UVM Verification of an ALU☆13Jun 14, 2024Updated 2 years ago
- Static Timing Analysis Full Course☆76Jan 14, 2023Updated 3 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆15Jul 28, 2021Updated 5 years ago
- System Verilog BootCamp☆66Jan 21, 2022Updated 4 years ago
- ☆10Oct 16, 2023Updated 2 years ago
- ☆58Jun 19, 2021Updated 5 years ago
- Verilog implementation of Pac-Man made for a class's final project☆19Mar 7, 2012Updated 14 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- The Soldier Health Monitoring and Position Tracking System allows the military personnel to track the current GPS position of a soldier a…☆12Dec 27, 2021Updated 4 years ago
- Verilog Project☆24Aug 30, 2021Updated 5 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆40Nov 6, 2022Updated 3 years ago
- ☆18Jun 12, 2023Updated 3 years ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- DMA Project using Verilog HDL☆15Dec 26, 2019Updated 6 years ago
- Using an Altera DE10-Lite FPGA development board to simulate an FFT processor. Audio input frequencies will be visualized onto a VGA disp…☆17May 5, 2020Updated 6 years ago
- RTL Design and Verification☆23Jan 4, 2021Updated 5 years ago
- Vitis-AI 1.3 TensorFlow2 flow with a custom CNN model, targeted ZCU102 evaluation board.☆15Apr 6, 2021Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Engineering Program on RTL Design for FPGA Accelerator☆36Aug 1, 2020Updated 6 years ago
- This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…☆24Mar 2, 2023Updated 3 years ago
- a hardware task scheduler design☆10Sep 14, 2022Updated 4 years ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆22Aug 6, 2025Updated last year
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆57Aug 1, 2026Updated 2 months ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆21Dec 8, 2012Updated 13 years ago
- Scene Understanding in autonomous driving by sensor fusion. Detected vehicles and 3D objects from LiDAR sensor range images by building …☆11Apr 15, 2023Updated 3 years ago
- Simple single-port AXI memory interface☆51Jun 7, 2024Updated 2 years ago
- ☆19Jun 3, 2019Updated 7 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- APB Timer Unit☆14Oct 30, 2025Updated 11 months ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆16Jan 13, 2015Updated 11 years ago
- ☆13May 22, 2015Updated 11 years ago
- Submission template for Tiny Tapeout 9 - Verilog HDL Projects☆15Nov 13, 2024Updated last year
- The STM32F4 has the SMC speed control, this microcontroller recives the Hall efect sensors signals of motor Brushless and the digital val…☆14May 20, 2020Updated 6 years ago
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆18Sep 12, 2023Updated 3 years ago
- Generic AXI master stub☆20Jul 17, 2014Updated 12 years ago