MIPSfpga+ allows loading programs via UART and has a switchable clock
☆112Jun 27, 2019Updated 6 years ago
Alternatives and similar repositories for mipsfpga-plus
Users that are interested in mipsfpga-plus are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- CPU microarchitecture, step by step☆207Nov 1, 2020Updated 5 years ago
- Digital Design Labs☆25Dec 21, 2018Updated 7 years ago
- Репозиторий факультатива по функциональной верификации НИУ МИЭТ☆16Aug 24, 2024Updated last year
- Repository gathering basic modules for CDC purpose☆60Dec 31, 2019Updated 6 years ago
- Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.☆19Jul 29, 2021Updated 4 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- This repository contains synthesizable examples which use the PoC-Library.☆39Dec 24, 2020Updated 5 years ago
- GDB interface utility for MIPS processors, including PIC32☆26Sep 20, 2019Updated 6 years ago
- CPU microarchitecture, step by step☆187Jun 26, 2022Updated 3 years ago
- FPGA examples for 8bitworkshop.com☆30May 23, 2019Updated 6 years ago
- ☆25May 20, 2020Updated 5 years ago
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆26Dec 5, 2024Updated last year
- Verilog Repository for GIT☆35May 4, 2021Updated 4 years ago
- EDA Tools: Xilinx ISE 14.7 Dockerfile☆20Jun 20, 2022Updated 3 years ago
- Example of Python and PyTest powered workflow for a HDL simulation☆15Jan 17, 2021Updated 5 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ZPUino HDL implementation☆91Aug 6, 2018Updated 7 years ago
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆13Sep 22, 2025Updated 6 months ago
- The original high performance and small footprint system-on-chip based on Migen™☆343Jan 5, 2026Updated 2 months ago
- crap-o-scope scope implementation for icestick☆20Jun 1, 2018Updated 7 years ago
- A fork of v7x86☆17Oct 22, 2022Updated 3 years ago
- A small RISC-V core (SystemVerilog)☆33Aug 26, 2019Updated 6 years ago
- Algol 60 compiler for Electrologica X1, restored☆15Jul 27, 2025Updated 8 months ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆36Dec 24, 2020Updated 5 years ago
- Core description files for FuseSoC☆125Jun 26, 2020Updated 5 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- JTAG DPI module for OpenRISC simulation with Verilator☆18Oct 27, 2012Updated 13 years ago
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Dec 6, 2019Updated 6 years ago
- RISCV implementation in Verilog (RV32I spec)☆18Nov 5, 2025Updated 4 months ago
- A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, …☆48Jun 14, 2023Updated 2 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆970Nov 15, 2024Updated last year
- A reconfigurable and extensible VLIW processor implemented in VHDL☆39Mar 14, 2015Updated 11 years ago
- SpaceWire☆14Jul 17, 2014Updated 11 years ago
- ☆11Jul 12, 2023Updated 2 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 8 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- LatticeMico32 soft processor☆106Oct 10, 2014Updated 11 years ago
- Emacs major mode for editing NAND hardware description language files (.hdl)☆14Nov 24, 2023Updated 2 years ago
- Simple OS for raspberry pi 2 model B☆13Jun 24, 2017Updated 8 years ago
- Implementation of a circular queue in hardware using verilog.☆17Mar 22, 2019Updated 7 years ago
- 586 compatible soft core for FPGA in verilog with AXI4 interface☆15Oct 15, 2016Updated 9 years ago
- RISC-V CPU Core☆417Jun 24, 2025Updated 9 months ago
- Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем☆22Mar 7, 2026Updated 2 weeks ago