Alternatives and similar repositories for mipsfpga-plus

Users that are interested in mipsfpga-plus are comparing it to the libraries listed below

• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆72Updated 7 years ago
• syntacore / scr1-sdk
  open-source SDKs for the SCR1 core
  ☆77Updated last year
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆131Updated 2 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆99Updated last year
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆45Updated 8 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆77Updated 9 months ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 6 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆71Updated 3 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 10 months ago
• m-labs / lm32
  LatticeMico32 soft processor
  ☆107Updated 11 years ago
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆124Updated 5 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆125Updated 9 years ago
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆130Updated 3 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆44Updated last month
• ZipCPU / vgasim
  A Video display simulator
  ☆175Updated 8 months ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆124Updated 2 years ago
• featherweight-ip / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 4 years ago
• MIPSfpga / schoolMIPS
  CPU microarchitecture, step by step
  ☆206Updated 5 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 7 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆186Updated last year
• CospanDesign / nysa-sata
  ☆89Updated 8 years ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆99Updated 6 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆86Updated last year
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆125Updated 5 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆97Updated 3 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆34Updated 9 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆69Updated last year
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago