MIPSfpga / mipsfpga-plusLinks
MIPSfpga+ allows loading programs via UART and has a switchable clock
☆112Updated 6 years ago
Alternatives and similar repositories for mipsfpga-plus
Users that are interested in mipsfpga-plus are comparing it to the libraries listed below
Sorting:
- Yet Another RISC-V Implementation☆99Updated last year
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆72Updated 7 years ago
- LatticeMico32 soft processor☆107Updated 11 years ago
- An Open Source configuration of the Arty platform☆131Updated 2 years ago
- open-source SDKs for the SCR1 core☆77Updated last year
- A single-wire bi-directional chip-to-chip interface for FPGAs☆125Updated 9 years ago
- CMod-S6 SoC☆45Updated 8 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆71Updated 3 years ago
- WISHBONE SD Card Controller IP Core☆130Updated 3 years ago
- Wishbone interconnect utilities☆44Updated last month
- Core description files for FuseSoC☆124Updated 5 years ago
- Verilog wishbone components☆124Updated 2 years ago
- A Video display simulator☆175Updated 8 months ago
- OpenRISC 1200 implementation☆178Updated 10 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- FuseSoC standard core library☆153Updated 2 months ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆125Updated 5 years ago
- ☆89Updated 8 years ago
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- A utility for Composing FPGA designs from Peripherals☆186Updated last year
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆97Updated 3 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆82Updated 6 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆97Updated 3 years ago
- Verilog implementation of a RISC-V core☆135Updated 7 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- The OpenRISC 1000 architectural simulator☆77Updated 9 months ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆72Updated 9 years ago
- ☆140Updated this week
- Featherweight RISC-V implementation☆53Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago