MIPSfpga / mipsfpga-plusLinks
MIPSfpga+ allows loading programs via UART and has a switchable clock
☆111Updated 6 years ago
Alternatives and similar repositories for mipsfpga-plus
Users that are interested in mipsfpga-plus are comparing it to the libraries listed below
Sorting:
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- An Open Source configuration of the Arty platform☆133Updated last year
- Verilog wishbone components☆119Updated last year
- Yet Another RISC-V Implementation☆98Updated last year
- CMod-S6 SoC☆42Updated 7 years ago
- Wishbone interconnect utilities☆42Updated 8 months ago
- open-source SDKs for the SCR1 core☆75Updated 11 months ago
- WISHBONE SD Card Controller IP Core☆128Updated 3 years ago
- Verilog implementation of a RISC-V core☆125Updated 7 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- FuseSoC standard core library☆147Updated 5 months ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆80Updated 6 years ago
- TCP/IP controlled VPI JTAG Interface.☆67Updated 9 months ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- SoftCPU/SoC engine-V☆55Updated 7 months ago
- LatticeMico32 soft processor☆107Updated 11 years ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆97Updated 3 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆122Updated 9 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- A utility for Composing FPGA designs from Peripherals☆185Updated 10 months ago
- A Video display simulator☆174Updated 5 months ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- CPU microarchitecture, step by step☆203Updated 4 years ago
- The OpenRISC 1000 architectural simulator☆74Updated 6 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆90Updated 3 years ago
- ☆39Updated 4 years ago
- JTAG Test Access Port (TAP)☆36Updated 11 years ago
- ☆137Updated 10 months ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆123Updated 5 years ago